Layout Pattern Decomposition for Double Patterning Lithography
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in efficiently decomposing and separating target feature patterns into two masks for the double patterning technique, particularly at sub-40 nm scales, where issues like line-edge roughness, shot noise, and resist collapse complicate the formation of precise patterns.
Innovation Solution
A layout pattern decomposition method that categorizes features into 1D and 2D types, calculates specific width sums and spaces, and compares these values against predetermined thresholds to color features systematically, assigning them to different patterns for precise mask formation in double patterning lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size and pitch are reduced to increase integration level, then device speed and performance are improved, but manufacturing difficulty and complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the target pattern into two separate color groups (first color and second color) that can be manufactured independently. This is achieved through the coloring step where features are assigned different colors based on their spatial relationships, enabling the complex sub-40nm pattern to be broken down into two manufacturable masks that avoid the limitations of direct single-exposure lithography
Solution Approach 2:
The patent transitions from a single-dimensional manufacturing approach to a two-dimensional solution by using dual-color patterning. Instead of attempting to create all features in one exposure, the method adds a color dimension where features are classified into first-color and second-color groups, each requiring separate mask fabrication and exposure steps, thereby overcoming the resolution limits of conventional single-step lithography
2Manufacturing precision
If feature size is reduced below 40 nm, then integration level increases, but line-edge roughness and resist collapse occur
Solution Approach 1:
The patent segments the pattern formation process into two separate exposure steps, each handling only first-color or second-color features. This segmentation allows each exposure to use optimized exposure conditions and resist formulations suitable for sub-40nm features, reducing the stress on any single exposure step and thereby minimizing line-edge roughness and resist collapse that would occur in a single high-density exposure
Solution Approach 2:
The patent applies local quality by allowing different regions of the pattern (first-color regions and second-color regions) to be manufactured with different process parameters. Each color group can be optimized independently for its specific geometric characteristics, enabling tailored exposure doses, focus settings, and resist conditions for different feature types and densities, thus improving overall pattern fidelity at sub-40nm scales
3Manufacturing precision
If features are decomposed into two colors and masks, then sub-40 nm features can be formed, but decomposition complexity increases
Solution Approach 1:
The patent implements self-service through the automated coloring algorithm that independently determines the color assignment of each feature based on its spatial relationships with neighboring features. The system automatically calculates edge-to-edge distances, identifies critical dimension violations, and assigns colors without requiring manual intervention or complex external decomposition tools, thereby managing the complexity of dual-color decomposition through self-contained automated rule-based logic
Data Source
AI summary
A layout pattern decomposition method includes following steps. A layout pattern is received. The layout pattern includes a plurality of features, and an edge-to-edge space is respectively defined in between two adjacent features. A sum of a width of the edge-to-edge space and a width of the feature on a left side of the edge-to-edge space and a sum of the width of the edge-to-edge space and a width of the feature on a right side of the edge-to-edge space are respectively calculated. The sums and a predetermined value are respectively compared. When any one of the sums is smaller than the predetermined value, the two features on the two sides of the edge-to-edge space are colored by a first color and alternatively a second color. The features including the first color are assigned to a first pattern and the features including the second color to a second pattern.