Layout Pattern Resizing for Semiconductor Process Window
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Solution Overview
Problem
Conventional optical proximity correction methods in photolithography do not effectively enhance the area size of layout patterns, such as contact holes or metal interconnections, which require larger areas for better operational performance, leading to suboptimal semiconductor device performance due to unchanged actual area sizes.
Innovation Solution
A method that determines a process window by resizing pattern data using a bias set of decreasing values, ensuring all polygons meet minimum spacing, contact to poly, and contact to metal rules, allowing for maximum area expansion while maintaining operational integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical proximity correction is applied to correct image distortion, then image quality is improved, but the actual area size of layout patterns remains unchanged
Solution Approach 1:
Instead of correcting image distortion as done in conventional OPC, this patent inverts the approach by intentionally resizing the layout patterns before lithography. The pattern data is enlarged using bias values so that after optical proximity effect and process variations, the final printed pattern achieves the desired area size and shape, thereby simultaneously improving image quality and actual area size.
Solution Approach 2:
The patent applies preliminary resizing action to the layout patterns before the lithography process. By pre-enlarging the patterns using bias values and performing area checks before manufacturing, the method proactively compensates for expected shrinkage and distortion, ensuring the final pattern meets area requirements without needing post-processing adjustments.
2Reliability
If layout patterns are enlarged to increase area size, then operational performance is improved, but spacing rules may be violated
Solution Approach 1:
The patent applies partial enlargement using bias values to specific polygons rather than uniformly enlarging all patterns. The area check function selectively applies bias to individual polygons, enlarging them just enough to achieve desired area size while performing spacing rule checks to prevent excessive enlargement that would violate manufacturing constraints. This partial action approach balances area enhancement with rule compliance.
Solution Approach 2:
The patent applies different bias values to different polygons based on their specific requirements. Rather than applying a uniform enlargement to all patterns, the method selectively enlarges individual polygons that need area enhancement while maintaining original sizes for patterns that already meet requirements, thereby locally optimizing area size without globally violating spacing rules.
Data Source
AI summary
A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output.