Layout Router Odd Loop Detection for DPT Compliance
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Solution Overview
Problem
Advanced semiconductor technology poses challenges in layout routing due to lithography limits, leading to undesirable odd loops when multiple nets are closely spaced, which existing layout routers struggle to detect and resolve effectively.
Innovation Solution
A layout router is configured to support odd loop detection by assigning pin loop values based on mask assignments, creating pin loops, and determining Double Patterning Technology (DPT) compliance or violations, using phantom assisted feature masks to compensate for pre-colored pins and internal conflict spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple nets are spaced closer than lithography limit, then routing density is improved, but odd loops are formed causing DPT violations
Solution Approach 1:
The layout router performs preliminary odd loop detection by creating pin loops and assigning pin loop values based on mask assignments before final routing completion. This preliminary action identifies potential DPT violations early, allowing corrective measures to be taken before the routing is finalized, thus preventing DPT violations while maintaining high routing density
Solution Approach 2:
The patent introduces pin loops as intermediary structures that connect pins through conflict spaces. By analyzing pin loop values (odd or even), the system mediates between the desire for close net spacing and DPT compliance requirements. The pin loop analysis acts as an intermediary check that resolves the contradiction by identifying when close spacing creates problematic odd loops
2Reliability
If odd loop detection is implemented for pre-colored pins, then DPT compliance is improved, but routing complexity increases
Solution Approach 1:
The layout router performs self-service by automatically detecting odd loops and assigning pin loop values without requiring external intervention. The system uses its existing routing information and conflict space data to autonomously identify DPT violations, reducing the need for additional complex detection mechanisms while improving DPT compliance
Solution Approach 2:
The patent changes the parameter analysis approach by introducing pin loop values (odd/even classification) based on mask assignments. This parameter transformation simplifies the complexity by converting complex geometric relationships into discrete odd/even classifications, making odd loop detection more manageable while improving DPT compliance
Data Source
AI summary
One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.