Semiconductor Layout Rule Enforcement With AI-Based Auto-Correction
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Solution Overview
Problem
The increasing complexity of semiconductor layout diagrams has led to a bottleneck in the design process due to the manual adjustment of design rule violations, slowing down the manufacturing process.
Innovation Solution
A system utilizing neural networks, including a convolutional neural network (CNN) for design rule checking and a reinforcement learning (RL) network for layout modification, automates the enforcement of design rules, reducing manual modifications and accelerating the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual adjustment of design rule violations is performed, then design rule compliance is achieved, but the design process speed decreases
Solution Approach 1:
The system enables automated self-correction of design rule violations through neural networks. The DRC module automatically detects violations and the LDM module automatically modifies the layout to correct them, eliminating the need for manual intervention and thereby maintaining design rule compliance while significantly improving design process speed
Solution Approach 2:
The patent replaces the manual mechanical process of design rule checking and layout modification with an automated electronic system based on neural networks. The DRC module uses a CNN to detect violations, and the LDM module uses an RL network to generate corrections, substituting human operators with intelligent algorithms to achieve both compliance and speed
2Adaptability or versatility
If the complexity of semiconductor layout diagrams increases, then device functionality is improved, but the difficulty of design rule enforcement increases
Solution Approach 1:
The system implements a feedback loop where the DRC module continuously monitors the layout for design rule violations, and the LDM module uses reinforcement learning to iteratively improve layout modifications based on the detected violations. This feedback mechanism enables the system to handle increasingly complex layouts by learning from each detection-correction cycle
Solution Approach 2:
The patent employs neural networks that can adapt to changing layout parameters and complexity levels. The DRC module's CNN and LDM module's RL network dynamically adjust their processing based on the input layout's characteristics, enabling effective design rule enforcement across varying levels of complexity without requiring manual reconfiguration
Data Source
AI summary
A system (for manufacturing a semiconductor device) includes an unvalidated subject layout diagram representing the semiconductor device, the system being configured to generate the following including: a feature extractor module configured to extract subject features that at least partially comprise the unvalidated subject layout diagram; and a design rule (DR) enforcement module including a DR checker (DRC) module and layout diagram modifier (LDM) module, the DRC module being configured to check the subject features for compliance with corresponding design rules in a set thereof and to identify which of the design rules are being violated and corresponding DR-violating subject features, and the LDM module being configured to attempt reducing the DR violations by modifying the DR-violating subject features resulting in a validated subject layout diagram; the DRC module being based on a first neural network; and the LDM module being based on a second neural network.