Full-Chip Layout Shell Structure for Stress Hotspot Detection
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Solution Overview
Problem
Current semiconductor device layout design processes are time-consuming and prone to errors, requiring numerous iterations and increasing manufacturing costs due to the inefficiencies in layout checking, particularly when using sampled layouts which may miss critical hotspots.
Innovation Solution
A layout check system and method utilizing a full-chip layout that preprocesses data to generate a layout shell structure and process condition model, performs stress simulations, and extracts statistics to accurately identify layout errors and defects, thereby reducing the likelihood of errors and shortening the design time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a sampled layout is used for layout checking, then the check time is reduced, but the accuracy of detecting layout errors and hotspots deteriorates
Solution Approach 1:
The full-chip layout is divided into multiple tiles, and stress simulation is performed on each tile separately. This segmentation allows the system to process large layouts in manageable units, reducing overall check time while maintaining full-chip coverage for accurate hotspot detection.
Solution Approach 2:
The patent transforms the traditional 2D layout representation into a 3D shell structure by adding height information that represents stress accumulation. This dimensional enhancement enables more accurate stress simulation and hotspot detection while efficiently processing the layout data.
2Measurement precision
If a full-chip layout is used for layout checking, then the accuracy of detecting layout errors and hotspots is improved, but the check time increases
Solution Approach 1:
The full-chip layout is divided into multiple tiles, and stress simulation is performed on each tile separately. This segmentation allows the system to process large layouts in manageable units, reducing overall check time while maintaining full-chip coverage for accurate hotspot detection.
Solution Approach 2:
The layout is preprocessed to generate a shell structure and identify regions of interest before performing stress simulation. This preliminary action reduces the complexity of the full-chip layout, enabling faster simulation while maintaining detection accuracy.
3Reliability
If multiple iterations of trial-and-error are performed in layout design, then the layout quality is improved, but the design time increases
Solution Approach 1:
Stress simulation and hotspot detection are performed early in the design process using the full-chip layout. This preliminary detection of potential issues allows designers to correct problems before manufacturing, reducing the need for iterative revisions and shortening overall design time.
Solution Approach 2:
The system provides feedback on stress distribution and hotspot locations through stress simulation results. This feedback mechanism enables designers to identify and correct layout issues systematically, improving layout quality while reducing the number of iterations required.
Data Source
AI summary
A layout check method includes generating a layout shell structure by preprocessing a full-chip layout, generating a process condition model by preprocessing at least one process condition, extracting a stress simulation value of the layout shell structure by performing a stress simulation based on the layout shell structure and on the process condition model, and extracting statistics data based on the stress simulation value of the layout shell structure, wherein the layout shell structure and the process condition model are configured to have a dimension which is greater than two dimensions and less than three dimensions.