Semiconductor Layout Testing for Parasitic Error Correction

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Solution Overview

Problem

As semiconductor devices shrink, process changes during manufacturing increase, leading to design challenges in predicting electrical characteristics and detecting errors like shorts, opens, component mismatches, and parameter mismatches, which affect manufacturing yield and chip operation.

Innovation Solution

A layout testing method that detects weak points in product layouts using pattern simulators, compares layout parameters with test wafers, and corrects electrical characteristic changes using an electrical characteristic change model, incorporating optical proximity correction (OPC) technology to ensure design rule compliance and normal circuit operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If semiconductor devices are reduced in size to increase integration, then device density and functionality are improved, but process changes and manufacturing errors increase

Engineering Contradiction:

Improvedevice integration densityVSAvoidprocess control accuracy

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent performs layout testing and electrical characteristic verification before actual manufacturing. By using pattern simulators and electrical characteristic change models to predict manufacturing outcomes in advance, the system identifies potential process errors and layout issues before production, allowing corrections to be made without incurring manufacturing costs or delays

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent establishes a feedback loop where layout parameters are extracted from both design data and test wafer data, compared against each other, and used to detect electrical characteristic changes. This feedback mechanism allows the system to continuously monitor and adjust layout parameters to compensate for process variations, maintaining manufacturing precision despite increased device density

Inventive Principle:

Principle #23Feedback

2Reliability

If traditional LVS checking is used to verify layout, then schematic correctness is confirmed, but electrical characteristic changes due to process variations cannot be detected

Engineering Contradiction:

Improveschematic verification accuracyVSAvoidelectrical characteristic detection accuracy

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The patent extends traditional LVS checking by introducing electrical characteristic parameters beyond basic connectivity verification. It extracts layout parameters such as contact area, wire length, and spacing, and compares these parameters between design and test data to detect electrical characteristic changes that traditional LVS would miss, thereby maintaining schematic verification while adding electrical characteristic detection capability

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent introduces an electrical characteristic change model as an intermediary between layout verification and manufacturing. This model translates physical layout parameters into electrical characteristic predictions, allowing the system to detect subtle electrical changes that result from process variations without requiring direct measurement of each manufactured device

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If layout parameters are not verified against test data, then manufacturing speed is maintained, but electrical characteristic deviations go undetected

Engineering Contradiction:

Improvemanufacturing throughputVSAvoidelectrical characteristic consistency

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent performs layout parameter extraction and comparison in advance, before actual device manufacturing. By using pattern simulators to predict electrical characteristics and comparing these predictions with test wafer data, the system identifies potential deviations early, allowing corrections to be made without slowing down the main manufacturing process

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent creates a self- verifying layout testing system that automatically extracts parameters, compares design data with test data, and detects electrical characteristic changes without requiring manual intervention. This automated process maintains manufacturing speed while ensuring electrical characteristic consistency through continuous verification

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS8356271B2Layout testing method and wafer manufacturing method

Publication Date: 2013.01.15 SAMSUNG ELECTRONICS CO LTD

AI summary

A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked.