Layout Variation Analysis for Integrated Circuit Simulation
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Solution Overview
Problem
Current integrated circuit (IC) design and manufacturing processes face challenges in efficiently simulating and identifying layout-related variations, leading to potential design failures and increased simulation time due to the need for extensive Monte Carlo modeling.
Innovation Solution
A system and method utilizing a device variation translator to translate individual variables of split devices into equivalent variables, allowing for targeted simulations in pre-simulation, re-simulation, and post-simulation phases, reducing simulation time by reusing identified samples and applying layout-related variations to modify IC layouts effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extensive Monte Carlo modeling is used to simulate layout-related variations, then measurement precision and reliability are improved, but simulation time and computational resources increase significantly
Solution Approach 1:
The patent segments the simulation process into multiple phases: initial simulation with standard parameters, identification of abnormal samples, and targeted re-simulation of only those abnormal samples with layout-related variations. This segmentation allows comprehensive analysis while minimizing total simulation time by avoiding redundant simulations of normal samples.
Solution Approach 2:
Instead of applying layout-related variations to all samples in a comprehensive Monte Carlo simulation, the patent applies these variations only to the subset of abnormal samples identified in the initial simulation. This partial action approach maintains measurement precision for critical cases while significantly reducing overall computational burden.
2Reliability
If comprehensive simulations are performed on all samples, then reliability of design validation is improved, but productivity and efficiency deteriorate due to extensive simulation requirements
Solution Approach 1:
The patent performs a preliminary simulation phase using standard device parameters before conducting detailed layout-related variation analysis. This preliminary action identifies abnormal samples that require further investigation, enabling subsequent simulations to focus only on critical cases and thereby improving overall design validation efficiency.
Solution Approach 2:
The patent introduces an intermediary filtering mechanism that identifies abnormal samples based on initial simulation results. This intermediary step acts as a gateway between comprehensive validation requirements and productivity constraints, directing detailed analysis only where necessary while maintaining overall design reliability.
3Manufacturing precision
If layout-related variations are applied to all devices, then manufacturing precision is improved, but use of computational resources increases unnecessarily
Solution Approach 1:
The patent applies layout-related variations locally only to abnormal samples rather than uniformly to all devices in the circuit. This local quality approach ensures manufacturing precision is maintained for critical samples while avoiding unnecessary computational resource consumption on samples that already meet design specifications.
Data Source
AI summary
A method is disclosed that includes performing a first simulation by applying first variations to identify at least one sample of an integrated circuit (IC), wherein the IC comprises at least one device; translating individual variables of split devices implementing the at least one device, to an equivalent variable for the split devices; and performing a second simulation, by applying at least a portion of second variations, with the equivalent variable for the split devices, to obtain a simulation result serving as a basis of modifying the layout for fabrication of the IC.