Semiconductor Layout Verification Using 3D Defocus Simulation
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Solution Overview
Problem
Current methods for verifying layout patterns in semiconductor manufacturing, such as optical proximity correction (OPC), fail to effectively detect and correct 3-Dimensional configuration defects like pattern collapse and film loss due to defocus issues, as they can only simulate images at the best exposure plane and not at top or bottom planes.
Innovation Solution
The method involves simulating layout patterns at both the lower and upper portions of a photoresist layer using the layout pattern as a mask, under negative and positive defocus conditions, to verify usability and correct defects by re-performing optical proximity correction when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional LRC method simulates image only at best exposure plane, then simulation process is simple, but 3-Dimensional configuration defects like pattern collapse and film loss cannot be detected
Solution Approach 1:
The patent extends the verification process from a single 2D plane (best focus plane) to multiple 3D planes (top plane, bottom plane, and best focus plane) within the photoresist layer. This dimensional expansion enables detection of 3-Dimensional defects such as pattern collapse and film loss that occur at different depths, transforming the verification capability from surface-level to volumetric analysis.
Solution Approach 2:
The photoresist layer is divided into multiple discrete planes (top plane, bottom plane, best focus plane) for separate simulation and verification. Each plane is independently analyzed to detect specific types of defects, allowing comprehensive 3D verification without requiring a single complex full-volume simulation, thus balancing detection capability with process complexity.
2Reliability
If multiple planes are simulated to detect 3D defects, then defect detection accuracy improves, but verification time and computational resources increase
Solution Approach 1:
The patent performs simulations at multiple planes (top, bottom, best focus) during the layout verification stage, before actual manufacturing. This preliminary multi-plane analysis identifies potential 3D defects early in the design phase, preventing costly manufacturing failures and reducing rework time, thereby improving overall verification efficiency despite increased initial computational effort.
Solution Approach 2:
The verification process creates simulated copies of the layout pattern at different planes within the photoresist layer. These virtual copies allow comprehensive 3D defect detection without requiring physical prototypes or multiple manufacturing iterations, reducing time and material costs while maintaining high verification reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the effective detection and correction of defects like pattern collapse and film loss, improving the accuracy of layout patterns and reducing yield loss by simulating 3-Dimensional patterns, which is crucial for advanced processes like the 45 nm technology node.
Implementation Method 1
In the photolithographic step, deviations occur and jeopardize the performance of the semiconductor device when the patterns on the reticles are transferred onto the wafer surface
Data Source
AI summary
A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns.