Layout Verification Netlist Comparison Without Rule Sets
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Solution Overview
Problem
The fabrication of integrated circuits is hindered by the complexity and cost of creating rule sets for device recognition engines in layout versus schematic (LVS) verification systems, which are necessary to identify devices and interconnects in graphical representations accurately, and there is a lack of equivalent verification systems for complex systems connected by wire bonds or circuit boards.
Innovation Solution
A method for operating a data processing system to detect layout errors by generating netlists from both schematic and graphical representations, comparing pin names and electrical properties, and removing extra devices or conductors to ensure consistency, without relying on complex rule sets, thereby simplifying the device recognition process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a device recognition engine uses a large complex rule set to identify devices and interconnects in graphical representations, then the accuracy of device and interconnect identification is improved, but the time and cost to create and maintain the rule set increases substantially
Solution Approach 1:
The patent extracts and removes the complex rule set from the device recognition engine, replacing it with a simplified approach that uses graphical representation features directly. This eliminates the need for extensive fabrication facility-specific rules while maintaining accurate device and interconnect identification through direct geometric and topological analysis of the graphical data.
Solution Approach 2:
The patent creates a simplified model of device recognition that copies the essential functionality without the complex rule set. Instead of using thousands of fabrication-specific rules, the system uses a universal approach that analyzes graphical representation features (shapes, positions, relationships) to identify devices and interconnects, achieving the same recognition accuracy without the time and cost overhead of rule set creation and maintenance.
2Reliability
If a device recognition engine uses a large complex rule set to identify devices and interconnects, then the reliability of layout verification is improved, but the device complexity of the verification system increases
Solution Approach 1:
The patent removes the complex rule set from the verification system, extracting only the essential graphical representation features needed for device and interconnect identification. This simplifies the verification system architecture while maintaining reliable layout verification through direct analysis of geometric shapes, positions, and topological relationships in the graphical data.
Solution Approach 2:
The patent creates a simplified verification system that copies the core functionality of device recognition without the complex rule set. The system uses universal graphical feature analysis instead of fabrication-specific rules, reducing device complexity while maintaining verification reliability through consistent and repeatable analysis of graphical representation features.
3Measurement precision
If extensive rule sets are used for device recognition in LVS verification, then the accuracy of netlist generation is improved, but the productivity of the fabrication process decreases
Solution Approach 1:
The patent extracts and eliminates the extensive rule set from the netlist generation process, replacing it with direct graphical feature analysis. This speeds up the netlist generation by avoiding the time-consuming creation and application of thousands of fabrication-specific rules, while maintaining accuracy through direct geometric and topological analysis of the graphical representation.
Solution Approach 2:
The patent creates a simplified netlist generation approach that copies the essential functionality without extensive rule sets. The system uses universal graphical feature analysis to identify devices and interconnects, generating accurate netlists faster by avoiding the productivity bottleneck of rule set processing while maintaining netlist generation accuracy.
Data Source
AI summary
A method for operating a data processing system to generate a layout for a netlist circuit based on a physical layout of that circuit is disclosed. A schematic of the circuit and an input defining a physical layout of the circuit are received by the data processing system. The schematic includes a plurality of schematic devices, characterized by unique schematic device names. The data processing system generates a graphical representation of the circuit from the physical layout, having one layout device corresponding to each of the plurality of schematic devices, each layout device being characterized by a graphical representation name that is the same as the schematic device name of the corresponding schematic device. First and second netlists are generated from the graphical representation and schematic, respectively. The data processing system generates a report specifying any differences in the first and second netlists.