Semiconductor Layout Width Bias Compensation for Multiple Patterning
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Solution Overview
Problem
In semiconductor fabrication, multiple-patterning technologies lead to variations in physical characteristics of features due to variations in mask formation processes, affecting the spatial resolution and electrical properties of fabricated components.
Innovation Solution
A method is introduced to generate a modified layout that models width variations caused by multiple patterning processes, using tables to determine width bias values based on the distance and width of components, allowing for accurate resistance-capacitance extraction and adjustment of layout patterns to compensate for these variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple-patterning technology is used to improve spatial resolution, then the spatial resolution of the layer is improved, but variations in physical characteristics of components occur due to mask formation process variations
Solution Approach 1:
The patent applies preliminary action by performing RC extraction simulations before actual fabrication to predict and identify width variations caused by multiple-patterning processes. The system pre-calculates bias values for different layout patterns based on simulated process variations, allowing designers to adjust layouts proactively before manufacturing, thus preventing the worsening of manufacturing precision while maintaining improved spatial resolution
Solution Approach 2:
The patent implements feedback by using RC extraction simulation results to generate width bias values that are fed back into the layout design process. The system continuously refines the layout by comparing simulated physical characteristics with target specifications, adjusting width parameters iteratively to compensate for anticipated process variations, thereby resolving the contradiction between improved spatial resolution and maintained manufacturing precision
2Manufacturing precision
If layout patterns are adjusted to compensate for variations, then manufacturing precision is improved, but the complexity of the design process increases
Solution Approach 1:
The patent applies self-service by implementing an automated system that performs RC extraction simulations, calculates width bias values, and generates modified layout patterns without requiring manual intervention. The system self-adjusts the layout parameters based on simulated process variations, automatically compensating for manufacturing precision issues while minimizing the increase in design process complexity through automation
Solution Approach 2:
The patent utilizes parameter changes by systematically varying width parameters of layout patterns based on calculated bias values. The system modifies specific geometric parameters (widths) of different layout features according to pre-determined correction factors, enabling precise control over physical characteristics while maintaining a structured and manageable design process that doesn't excessively increase complexity
Data Source
AI summary
A method, of generating a modified layout based on an original layout, includes: determining a first set of width bias values of an i-th set of layout patterns which compensate for subtractive process effects, the original layout having N sets of layout patterns corresponding to N masks; determining a second set of width bias values of the i-th set of layout patterns of the original layout which compensate for additive process effects; generating the modified layout based on the first and second sets of width bias values of the i-th set of layout patterns, the order index i of the i-th mask corresponding to an order of the i-th mask being applied during a fabrication process; and fabricating, based on the modified layout, at least one of a semiconductor mask or at least one component in a layer of an inchoate semiconductor integrated circuit.