Lazy Capability Revocation in Memory Systems

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Solution Overview

Problem

Existing memory management systems face inefficiencies in revoking capabilities when memory is deallocated, as they require complex tracking mechanisms to manage both original and derived capabilities, leading to costly and time-consuming operations.

Innovation Solution

Implementing a lazy revocation approach where derived capabilities are checked for validity only when used, allowing the memory controller to generate an exception if the referenced master capability is revoked, thus simplifying the revocation process and reducing the impact on data retrieval time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If linked list or chains of pointers are used to track all derived capabilities, then all derived capabilities can be found and revoked, but revocation becomes costly and complex

Engineering Contradiction:
Improvecapability revocation completenessVSAvoidrevocation mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the tracking complexity from the revocation mechanism itself and places it in the capability validation process. Instead of actively tracking derived capabilities through linked lists, the system validates each capability against the master capability at access time, removing the need for complex tracking structures while ensuring revocation completeness.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the traditional approach by not trying to find and revoke all derived capabilities actively, but rather by having the master capability validation passively invalidate any derived capabilities that reference it. The burden of tracking is shifted from the revocation mechanism to the access validation mechanism.

Inventive Principle:
Principle #13The other way round (Inversion)

2Productivity

If all derived capabilities are tracked and revoked immediately, then memory can be reallocated promptly, but the tracking and revocation operation becomes time-consuming

Engineering Contradiction:
Improvememory reallocation speedVSAvoidrevocation time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent performs preliminary validation by embedding the master capability reference in each derived capability and validating it at access time. This preliminary setup eliminates the need for time-consuming active tracking and immediate revocation, as capabilities are invalidated automatically when their master capability is revoked.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The derived capabilities essentially self-validate by checking their master capability reference during access. When the master capability is revoked, any attempt to use a derived capability automatically fails validation, eliminating the need for external tracking and manual revocation of each derived capability.

Inventive Principle:
Principle #25Self-service

3Reliability

If capability validation is performed on every memory access, then security and correctness are ensured, but data retrieval time increases

Engineering Contradiction:
Improvecapability validation correctnessVSAvoidmemory access speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent performs only the essential partial validation needed for security - checking whether the derived capability's address range falls within the master capability's range. This minimal validation approach ensures correctness while minimizing the performance overhead compared to more comprehensive validation schemes.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10387335B2Memory system and handles to master capabilities
Publication Date: 2019.08.20 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10387335B2 patent drawing
  • US10387335B2 patent drawing
  • US10387335B2 patent drawing

AI summary

In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to receiving the memory access request, a memory controller checks whether the handle references a valid master capability and checks whether the data capability is within a scope of the master capability. In response to determining that the master capability is valid and the data capability is within the scope of the master capability, the memory controller returns a result of the memory access request to the processor.