LBIST Clock Gating Circuit for Accurate Scan Capture
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Solution Overview
Problem
Existing logic built-in self-test (LBIST) techniques face issues with unreliable and inaccurate test coverage due to randomly generated signals, which hinder the detection of defects in semiconductor devices, especially during system operation without external storage.
Innovation Solution
A logic BIST circuit with improved test coverage and low-power capabilities, utilizing clock gating circuits and modified scan enable signals to ensure accurate capture of output data in scan chains, irrespective of function enable signals, and incorporating decompressors, pattern counters, and pulse generators to generate test patterns and control clock gating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If random signal generation is used in LBIST, then test coverage is improved, but reliability and accuracy of tests deteriorate
Solution Approach 1:
The patent changes the parameter of signal generation from random to deterministic sequence-based. The test signal generator produces sequences according to predefined rules (e.g., m-sequence generators), transforming the test approach from random parameter generation to controlled sequence parameter changes, thereby improving both coverage and reliability
2Ease of operation
If clock gating is controlled by function enable signals only, then normal operation is maintained, but test accuracy during capture sections deteriorates
Solution Approach 1:
The patent introduces dynamic control of clock gating by adding a scan enable signal dimension. The clock gating circuit now responds to both function enable signals and scan enable signals, allowing the system to dynamically switch between normal operation mode (function enable only) and test mode (scan enable overrides), thereby improving test accuracy without compromising normal operation
Solution Approach 2:
The patent introduces an intermediary control mechanism where the scan enable signal acts as a mediator that overrides the function enable signal during test sequences. This intermediary control allows the clock gating circuit to prioritize test capture requirements over normal operation requirements, ensuring accurate test measurement while maintaining ease of normal operation
3Device complexity
If scan test is performed without modified scan enable signals, then circuit simplicity is maintained, but test coverage for clock domains deteriorates
Solution Approach 1:
The patent segments the scan test control into separate OR gates for each clock domain, where each OR gate independently combines scan enable signals with function enable signals. This segmentation allows each clock domain to be tested independently with appropriate scan enable control, improving test coverage while keeping each domain's control logic simple and modular
Data Source
AI summary
A test clock gating circuit is provided. The test clock gating circuit is configured to: receive a clock and output an enable clock in response to a modified scan enable signal and a function enable signal; and determine whether to output the enable clock based on the logic value of the function enable signal when the modified scan enable signal is a first logic value/ The modified scan enable signal is generated based on a scan enable signal and a register setting signal.