Isolating Failing Latches in LBIST Using Segmented Scan Chains
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Solution Overview
Problem
Current logic built-in self-test (LBIST) circuitry in integrated circuits cannot identify which latch is failing, as it only determines if the entire circuit is defective, failing to distinguish between real physical failures and side effects from other failing components due to data corruption.
Innovation Solution
A method and device that utilize a set of expected values for scan chains associated with a failing multiple input signature register, initiating a test sequence, comparing outputs to these values, and incrementing a counter to pinpoint the failing latch by matching or mismatching the output values, allowing for the identification of the failing latch within the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current LBIST circuitry is used to test the integrated circuit device, then the test coverage is high, but the ability to identify specific failing latches is lost
Solution Approach 1:
The patent divides the scan path into multiple scan chains and further segments the testing process into multiple test portions. By comparing outputs at different segments and using a data structure to track expected versus actual values, the system can isolate which specific latch is failing rather than only determining that the entire circuit is defective.
Solution Approach 2:
The patent introduces a data structure as an intermediary between the multiple input signature register and the final defect identification. This data structure stores expected values and enables comparison with actual outputs, serving as a mediator that translates raw test data into actionable defect location information.
2Reliability
If LBIST tests all logic in the integrated circuit device, then comprehensive testing is achieved, but the complexity of analyzing which specific component failed increases
Solution Approach 1:
The patent segments the comprehensive test into multiple manageable test portions associated with different scan chains. Each test portion can be independently analyzed, reducing the complexity of identifying the specific failing component while maintaining complete coverage of all logic.
Solution Approach 2:
The patent implements a feedback mechanism where the output of the multiple input signature register is continuously compared against expected values stored in the data structure. This feedback loop enables real-time identification of deviations, simplifying the analysis of which specific latch is failing without requiring complex post-test analysis.
3Ease of operation
If the entire integrated circuit device is tested as a unit, then the testing process is simple, but the ability to distinguish real physical failures from side effects is reduced
Solution Approach 1:
The patent maintains testing simplicity by keeping the overall LBIST framework intact while introducing segmented analysis through multiple scan chains and test portions. This segmentation enables distinction between real physical failures and side effects from other failing components without significantly complicating the testing process.
Solution Approach 2:
The data structure serves as an intermediary that stores expected values and enables detailed comparison with actual test outputs. This intermediary layer provides the additional analysis capability needed to distinguish failure types while maintaining the simplicity of the overall testing operation.
Data Source
AI summary
A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.