LBIST Scan Chain Defect Diagnostics via Frequency Comparison
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Diagnosing transitional, delay, or AC scan chain defects in VLSI testing is challenging due to the difficulty in rapidly localizing defects to a specific location, which affects manufacturing yield and revenue, as existing methods are inefficient and unable to provide rapid defect isolation for Physical Failure Analysis.
Innovation Solution
The method employs structural Logic Built In Self Test (LBIST) test patterns applied across multiple frequencies and voltage conditions, comparing unload data from passing and failing operating regions to identify potential AC defective latches, which are then sent to Physical Failure Analysis, using a good machine simulator to pinpoint the defective latch causing the transitional scan chain failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional diagnostic methods are used for scan chain defects, then the testing process is simple, but the defect localization speed is slow and manufacturing yield is reduced
Solution Approach 1:
The patent divides the scan chain into multiple segments by inserting diagnostic logic at specific points. This segmentation allows the testing system to isolate and identify defective latches more quickly by testing segments rather than the entire chain, thereby improving defect localization speed without requiring complete retesting of the whole system.
Solution Approach 2:
The patent introduces diagnostic logic and additional test signals as intermediary elements between the test stimulus and the scan chain latches. These intermediaries provide extra measurement points and diagnostic information that enable faster defect identification, trading some additional circuit complexity for significant improvements in diagnostic speed and accuracy.
2Reliability
If rapid defect isolation is implemented, then manufacturing yield improves, but the testing process becomes more complex
Solution Approach 1:
The patent implements preliminary diagnostic actions by pre-configuring the scan chain with diagnostic logic and pre-planning test sequences that target potential defect locations. This preliminary preparation enables rapid defect isolation when failures occur, improving manufacturing yield by quickly identifying bad devices, while the complexity is managed through systematic pre-configuration rather than ad-hoc testing.
Solution Approach 2:
The patent incorporates feedback mechanisms where diagnostic test results are immediately analyzed and used to guide subsequent testing actions. This feedback loop enables rapid iteration and quick identification of defective latches, improving reliability by reducing the time to isolate defects. The feedback-driven approach manages complexity by focusing testing resources only on suspect areas rather than exhaustive testing.
3Measurement precision
If LBIST test patterns are applied across multiple frequencies and voltage conditions, then diagnostic accuracy improves, but testing time increases
Solution Approach 1:
The patent applies partial testing by selecting specific frequency and voltage conditions that are most critical for detecting the particular defect types being tested. Rather than exhaustively testing all possible conditions, the method focuses on the most diagnostic subsets, achieving sufficient accuracy for defect identification while reducing overall testing time by omitting less critical test conditions.
Data Source
AI summary
A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.