LBIST Architecture with Separate Test Storage for Parallel Operation
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Solution Overview
Problem
Conventional Logic Built-In Self-Test (LBIST) architectures for integrated circuits disrupt normal operation, requiring system resets and reinitializations, leading to significant availability issues, especially in safety-critical systems like those in the vehicle sector, where continuous operation is essential.
Innovation Solution
A nondestructive LBIST architecture with a separate stimulation and response path allows for parallel operation with normal system functions, enabling test data loading during work mode without disturbing the system, using a Self-Test Using MISR and Parallel Shift Register Sequence Generator (STUMPS) architecture that maintains storage element states, allowing seamless continuation of normal operation post-testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LBIST architecture is used, then logic errors can be detected, but normal operation is disrupted requiring system reset and reinitialization
Solution Approach 1:
The patent divides the storage elements into two separate groups: functional storage elements that maintain system operation data, and test storage elements that hold LBIST test data. This segmentation allows independent operation of testing and functional modes, enabling LBIST execution without disrupting normal system functionality and eliminating the need for system resets.
Solution Approach 2:
The patent extracts the test data storage function from the functional storage elements by providing separate test storage elements. These dedicated test storage elements can be loaded with test patterns and used for LBIST operations independently, allowing the functional storage elements to maintain system state without interference from test operations.
2Reliability
If LBIST is performed during normal operation, then continuous monitoring is enabled, but system state is overwritten requiring reinitialization
Solution Approach 1:
The patent segments storage elements into functional and test groups, allowing LBIST operations to proceed in parallel with normal system operation. The test storage elements can be loaded with new test patterns while functional storage elements continue processing, enabling continuous fault detection without system downtime or reinitialization.
Solution Approach 2:
The patent enables continuous LBIST operation by maintaining separate test storage elements that can be continuously loaded with test patterns and used for ongoing testing. This allows the useful action of fault detection to continue uninterrupted alongside normal system operation, eliminating downtime between test cycles.
3Reliability
If separate test storage elements are provided, then nondestructive testing is enabled, but device complexity increases
Solution Approach 1:
The patent designs test storage elements that can serve dual purposes: storing test patterns for LBIST operations and potentially serving as functional storage elements when not in test mode. This multi-functionality reduces the overall complexity increase by allowing shared resources rather than completely separate dedicated structures.
Solution Approach 2:
The patent implements dynamic control mechanisms that can switch between functional mode and test mode, allowing the storage element architecture to adapt its configuration based on operational requirements. This dynamic switching capability manages complexity by providing a unified structure that can perform multiple functions rather than requiring permanently separate static structures.
Data Source
AI summary
An integrated circuit with self-test circuit is provided. The integrated circuit includes at least one logic circuit, at least one input storage element for storing work data, at least one output storage element, an input test storage element for storing test data, and at least one output test storage element, wherein the logic circuit is selectively connected to the input storage element on the input side, such that the input storage element provides the work data to the logic circuit, or is connected to the input test storage element on the input side, such that the input test storage element provides the test data to the logic circuit, wherein the logic circuit is further connected to the output storage element and the output test storage element on the output side, such that the logic circuit feeds data to the output storage element and/or to the output test storage element, and wherein the output storage element is configured to process the data from the logic circuit if the work data are provided to the logic circuit, and not to process the data from the logic circuit if the test data are provided to the logic circuit.