LBN Prefetching Cache Mediator for CPU Collision Avoidance
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Solution Overview
Problem
In multiprocessor hard drive or SSD environments, existing prefetching methods lead to inefficiencies due to overlapping data requests across processors, resulting in increased overhead and latency when host devices request data at LBA granularity, which is a subset of LBN granularity, causing collisions and suboptimal data retrieval.
Innovation Solution
A method and system that prefetch data from multiple CPUs and store it in cache memory, allowing for efficient data retrieval by determining whether data is scheduled for cache writing, delaying requests if necessary, and delivering data from cache to the host device, thereby reducing read latency and avoiding collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processors prefetch data simultaneously using master assignment or hardcoded ranges, then data prefetching capability is improved, but processor collisions and data retrieval overhead increase when host requests at LBA granularity
Solution Approach 1:
The patent introduces a cache memory as an intermediary layer between the storage device and host device. The cache stores prefetched data blocks, allowing the host to retrieve data quickly from the cache rather than waiting for processor coordination or direct storage access. This mediator resolves the collision problem by providing a centralized fast-access buffer that multiple processors can serve without direct conflicts.
Solution Approach 2:
The system performs preliminary data prefetching operations before the host actually requests the data. The controller predicts future host read requests and prefetches corresponding data blocks into the cache in advance. This preliminary action ensures that when the host requests data at LBA granularity, the data is already available in the cache, eliminating retrieval latency.
2Productivity
If data is read at LBN granularity from storage, then storage read efficiency is improved, but host requests at LBA granularity cause overlapping reads across processors increasing overhead
Solution Approach 1:
The patent segments the storage space into logical block units (LBUs) that are mapped to physical blocks. Each processor is assigned specific LBU ranges for prefetching, creating clear boundaries that prevent overlapping reads. This segmentation allows efficient storage-level parallelism while avoiding conflicts at the host interface level, as the cache handles LBA-to-LBU mapping transparently.
Data Source
AI summary
The present disclosure generally relates to prefetching data from one or more CPUs prior to the data being requested by a host device. The prefetched data is prefetched from memory and stored in cache. If a host device requests data that is not already in cache, then a determination is made regarding whether the data is scheduled to be written into cache. If the data is not in cache and is not scheduled to be written into cache, then the data is retrieved from memory and delivered to the host device. If the data is scheduled to be written into cache, or is currently being written into cache, then the request to retrieve the data is delayed or scheduled to retrieve the data once the data is in cache. If the data is already in cache, the data is delivered to the host device.