Liquid Crystal Control Circuit Timing Offset for MIP Panels
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Solution Overview
Problem
In liquid crystal panels with memory elements, such as MIP panels, the timings for applying VCOM inversion signals and image data signals often overlap, leading to competition that can prevent normal image writing, necessitating precise timing control to avoid this interference.
Innovation Solution
A liquid crystal control circuit that holds off outputting the enable signal before and after the polarity inversion of AC voltage and secures a period for the enable signal output to prevent competition between VCOM inversion timing and image data reflection timing by managing the VCOM inversion flag and enable signal output periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If VCOM inversion timing and image data signal timing are synchronized, then device complexity is reduced, but image writing fails due to signal competition
Solution Approach 1:
The control circuit performs preliminary timing offset adjustment between VCOM inversion signals and image data signals during the initialization phase. By pre-calculating and setting the optimal timing offset before normal operation, the system avoids signal competition without requiring complex real-time timing control, thus maintaining reliability while keeping device complexity low.
Solution Approach 2:
A timing offset register acts as an intermediary component between the VCOM inversion signal generator and the image data signal generator. This register stores and manages the timing offset value, mediating the synchronization between the two signal streams and preventing direct competition while maintaining simple control logic.
2Reliability
If VCOM inversion timing is adjusted to avoid image data reflection timing, then image writing reliability is improved, but timing control complexity increases
Solution Approach 1:
The system performs preliminary timing offset configuration during initialization or factory calibration, storing the optimal offset value in a register. This upfront action eliminates the need for complex real-time timing adjustment mechanisms, achieving reliable image writing with minimal ongoing control complexity.
Solution Approach 2:
The invention changes the timing parameter (phase offset) of the VCOM inversion signal relative to the image data signal. By adjusting this single parameter rather than redesigning the entire timing control system, the patent achieves reliable operation with minimal increase in device complexity.
3Reliability
If timing control is implemented to prevent signal competition, then image writing reliability is improved, but power consumption increases due to additional control operations
Solution Approach 1:
The timing offset is configured once during initialization or manufacturing, and then maintained statically during normal operation. This preliminary setup eliminates the need for continuous active timing adjustment, minimizing additional power consumption while ensuring reliable image writing throughout the device's operation.
Solution Approach 2:
The timing control operates periodically only during initialization or calibration phases, then transitions to a static state during normal display operation. This periodic rather than continuous operation significantly reduces the power overhead associated with timing control while maintaining image writing reliability.
Data Source
AI summary
A liquid crystal controller is provided for a liquid crystal panel having a plurality of pixels, each of which includes a memory element and a display element. The memory element is configured to hold electric potential depending on an image signal and is configured to change the held electric potential based on activation of an enable signal. The display element is configured to be applied voltage depending on the electric potential which the memory element holds. The liquid crystal controller is configured to: hold off outputting the enable signal, for a period th before polarity of AC voltage applied to the display element is inverted and a period (tr+ts) after the polarity of the AC voltage is inverted; and hold off inversion of the polarity of the AC voltage, for an output period of the enable signal and the period th after the output period.