Liquid Crystal Drive Circuit Power Management
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Solution Overview
Problem
Conventional liquid crystal driving devices with two oscillation circuits operate independently, leading to inefficiencies in power saving and potential image writing issues due to unsynchronized polarity reversal and image rewriting, while existing power-saving solutions do not address the need for continuous power supply in liquid crystal panels with pixel memory.
Innovation Solution
A drive circuit with a master-slave relationship between a low-speed and high-speed oscillation circuit, where the high-speed oscillation circuit operates only when image updates are necessary, and the power supply adjusts its capability accordingly to minimize power consumption during still image display.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the high-speed oscillation circuit operates constantly to supply the low-speed clock signal, then the low-speed clock signal can be continuously supplied to the power supply circuit and polarity-reversed signal output section, but excessive power is consumed during still image display
Solution Approach 1:
The patent applies dynamics by making the operation state of the high-speed oscillation circuit changeable based on display content. The circuit operates at high speed during image rewriting and transitions to low-speed operation during still image display, dynamically adapting its performance to current needs rather than maintaining constant high-speed operation
Solution Approach 2:
The patent implements periodic action by alternating between high-speed operation (during image updates) and low-speed operation (during still image display). This periodic switching of operational modes allows the system to consume power only when necessary for image rewriting while maintaining reliability through periodic reactivation
2Ease of operation
If two oscillation circuits operate independently, then each circuit can function autonomously, but power saving efficiency is reduced and image writing may be affected due to unsynchronized polarity reversal
Solution Approach 1:
The patent merges the control of two oscillation circuits through a unified control mechanism that coordinates their operations. The control section synchronizes the high-speed and low-speed oscillation circuits, ensuring their operations are coordinated rather than independent, which improves power saving efficiency while preventing image writing issues through synchronized polarity reversal
3Use of energy by stationary object
If the high-speed oscillation circuit is stopped during still image display, then power consumption is reduced, but the low-speed clock signal cannot be supplied to maintain the power supply circuit operation
Solution Approach 1:
The patent applies dynamics by enabling the high-speed oscillation circuit to switch between two operational speeds based on display requirements. During still image display, the circuit operates at low speed to maintain power supply circuit functionality while consuming minimal power, and transitions to high speed when image rewriting is required
Data Source
AI summary
Provided is a drive circuit including: an image supply section for supplying an image to be displayed on a liquid crystal panel (2); a command issuing section for issuing a command that instructs an image displayed on the liquid crystal panel (2) to be updated; a low-speed oscillation circuit (13) for supplying a low-speed clock signal (L-CLK); a high-speed oscillation circuit (8) for supplying a high-speed clock signal (H-CLK) higher in frequency than the low-speed clock signal (L-CLK); image outputting means for supplying, to the liquid crystal panel (2), the image from the image supplying means, the image outputting means being driven by the high-speed clock signal (H-CLK); and a logic section (10) for controlling, in accordance with the command issued by the command issuing section, whether or not to cause the high-speed oscillation circuit (8) to operate, the logic section (10) being driven by the low-speed clock signal (L-CLK).