LC Module Layout for 3D Memory Etch Windows
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Solution Overview
Problem
Existing three-dimensional semiconductor memory structures face challenges due to large discontinuities between adjacent conducting surface levels, leading to compromised critical dimensions and unwanted etch-through issues during manufacturing.
Innovation Solution
A three-dimensional semiconductor memory structure is formed using a plurality of LC modules with alternating conducting and insulating material layers, where the height difference between adjacent levels does not exceed two OP layer pairs, achieved through a method involving specific etch positions and sequences to create distinct surface levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If sequential mask/photo/etch steps are performed with photoresist being incrementally peeled back between etch steps to create multiple staircase structures, then three-dimensional memory structures can be formed, but large discontinuities are created between levels of adjacent surfaces compromising critical dimensions and creating etch-through issues
Solution Approach 1:
The patent divides the formation process into two distinct phases: first forming complete staircase structures with all conducting and insulating layers, then performing a single etch process to create contact openings. This segmentation eliminates the need for incremental photoresist peeling between multiple etch steps, thereby preventing large discontinuities between adjacent surface levels and maintaining critical dimension control.
2Productivity
If the number of etch steps is increased to create more staircase structures, then memory density increases, but large discontinuities between adjacent surfaces are created reducing contact patterning overlay margin
Solution Approach 1:
The patent performs the preliminary action of forming complete staircase structures with all conducting and insulating layers before performing the contact opening etch process. By establishing the full three-dimensional structure first, the method ensures that subsequent etching occurs on a stable, complete structure, preventing large discontinuities between adjacent surfaces even as memory density increases through additional layers.
3Shape
If monotonically increasing depth etches are performed to create multiple staircase levels, then three-dimensional structure is achieved, but unwanted etch-through issues occur
Solution Approach 1:
The patent segments the manufacturing process into structure formation and contact opening creation as separate operations. The staircase structures are fully formed with all conducting and insulating layers complete, then a single controlled etch process creates contact openings. This eliminates the cumulative effect of multiple incremental etches that cause etch-through, while still achieving the required three-dimensional structure.
Data Source
AI summary
A lay-out arrangement for LC modules in 3D semiconductor memories is described that avoids large step height. The arrangement creates insulating/conducting layer pairs with adjacent pairs differing in height by no more than the thickness of two insulating/conducting layer pairs.