LC Oscillator Phase Realignment for Low-Noise PLL Circuits
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Solution Overview
Problem
LC oscillators in digital phase locked loop circuits exhibit poor phase noise performance, especially in modern advanced processes with small feature sizes, and conventional solutions lead to larger device sizes and higher power consumption.
Innovation Solution
The use of realignment techniques involving high-quality clock signals with low phase noise, converted into pulse signals to control realignment circuits coupled to the LC oscillator terminals, which align the phase and address phase noise issues without increasing device size or power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional solutions are used to improve phase noise performance in LC oscillators, then phase noise performance is improved, but device size increases and power consumption increases
Solution Approach 1:
A realignment circuit is introduced as an intermediary component between the reference clock and the LC oscillator. This circuit receives a high-quality reference clock signal and generates realignment signals that are coupled to the LC oscillator terminals, thereby improving phase noise performance without requiring changes to the core oscillator structure or increasing device size
Solution Approach 2:
The realignment circuit performs preliminary phase alignment on the reference clock signal before it drives the LC oscillator. By pre-conditioning the reference signal with low-jitter characteristics and generating appropriately timed realignment signals, the system establishes optimal phase relationships in advance, preventing phase noise degradation before it occurs in the oscillator
2Reliability
If conventional solutions are used to improve phase noise performance in LC oscillators, then phase noise performance is improved, but power consumption increases
Solution Approach 1:
The realignment circuit serves as an energy-efficient intermediary that processes the reference clock signal separately from the main oscillator path. By using the existing high-quality reference clock and generating control signals through a dedicated realignment circuit rather than modifying the main oscillator, power consumption is minimized while achieving phase noise improvement
Solution Approach 2:
Phase alignment is performed preliminarily on the reference clock signal before it reaches the power-consuming LC oscillator. This preliminary processing ensures that the oscillator receives an already-optimized signal, reducing the need for additional power-consuming correction mechanisms within the oscillator itself
3Reliability
If realignment techniques are used to suppress in-band noise, then phase noise performance is improved, but circuit complexity increases
Solution Approach 1:
The realignment circuit is designed as a dedicated intermediary module with a specific function: to generate realignment signals from the reference clock. This separation of concerns isolates the complexity to a single functional block rather than distributing it throughout the entire oscillator system, making the overall architecture more manageable despite the added functionality
Solution Approach 2:
The realignment circuit performs multiple functions: it receives the reference clock, processes it to generate realignment signals, and couples these signals to the LC oscillator terminals. By consolidating these related functions into a single multi-functional block, the design achieves phase noise suppression without proportionally increasing overall circuit complexity
Data Source
AI summary
Oscillators and methods for realignment of an oscillator are provided. An oscillator includes an inductor having first and second terminals and a capacitor electrically coupled in parallel to the inductor at the first and second terminals. A first transistor of a first conductivity type is electrically coupled to the first terminal and a voltage source. The first transistor includes a gate configured to receive a first realignment signal. When the first realignment signal is in a realignment state, the first transistor is turned on and a voltage of the first terminal is increased from a low level to a high level in order to align a phase of a waveform of the oscillator.