LC Resonant Tank Clock Tree Synthesis for Power Reduction
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Solution Overview
Problem
Existing clock tree distribution networks in VLSI chips face challenges with uneven loading, which alters resonant behavior and increases power consumption, particularly due to parasitic resistances and inductances, and there is a need for a method to address these issues while enabling power efficiency and practical design topologies.
Innovation Solution
A computerized process for placing and sizing LC tanks in unbalanced clock tree distribution networks, considering local capacitance distributions and conductor resistances, allowing for automated design and significant power savings, using a novel algorithm that iteratively optimizes LC tank placement and sizing to maintain resonant behavior and minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If resonant clocks are used in clock distribution networks, then power consumption is decreased, but uneven loading and parasitic resistances alter resonant behavior and increase power consumption
Solution Approach 1:
The patent applies local quality by placing LC tanks at specific locations within the clock distribution network where they can compensate for local uneven loading conditions. Each LC tank is positioned to address the resonant behavior issues in its local region, allowing different parts of the network to have tailored compensation for their specific loading conditions and parasitic characteristics.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the values of inductance (L) and capacitance (C) in the LC tanks to optimize their compensating effect. By carefully selecting L and C values, the system can counteract the effects of parasitic resistances and uneven loading, maintaining stable resonant behavior while achieving power consumption reduction.
2Manufacturing precision
If H-tree clock distribution networks are used, then clock skew is minimized, but the topology is restricted and requires even distribution of gates and terminals
Solution Approach 1:
The patent applies asymmetry by moving away from the symmetric H-tree topology to an unbalanced clock tree structure. This allows the clock distribution network to adapt to uneven distributions of gates and terminals in the actual VLSI design, providing greater flexibility while still maintaining acceptable clock skew through strategic placement of LC tanks.
Solution Approach 2:
The patent uses segmentation by dividing the clock distribution network into multiple segments with LC tanks placed at different levels and positions. This segmentation allows each segment to be optimized independently for its local loading conditions, enabling the overall network to handle unbalanced gate distributions effectively.
3Use of energy by moving object
If LC tanks are placed in clock distribution network, then power consumption is reduced through energy recycling, but placement location determines attenuation and requires careful positioning
Solution Approach 1:
The patent applies preliminary action by performing automated analysis during the design stage to determine optimal LC tank placement locations. This preliminary optimization ensures that LC tanks are positioned before fabrication to achieve maximum power savings while accounting for the specific gate distribution and routing characteristics of the design, avoiding the need for manual trial-and-error placement.
4Reliability
If wire resistances are present in LC tank circuits, then resonance frequency shifts downward and Q changes, but resistances are unavoidable
Solution Approach 1:
The patent converts the harmful effect of parasitic resistances into a benefit by using the LC tanks to compensate for the frequency shifts and Q degradation caused by these resistances. The LC tanks are designed to counteract the detrimental effects of wire resistances, transforming the unavoidable parasitic elements from a problem into an opportunity for optimized resonant behavior through proper component selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables up to 80% power savings and allows for the practical implementation of resonant clock trees with asymmetric loads, enhancing the design of high-performance VLSI chips and reducing heat generation, making it suitable for devices like notebook computers and remote sensors.
Implementation Method 1
by oscillating clock energy between the electric field of capacitance Cs 12 and the magnetic field of inductor Ls 14 the clock energy is recycled and power consumption is decreased
Implementation Method 2
the electric field of capacitance Cs 12
Implementation Method 3
the magnetic field of inductor Ls 14
Data Source
AI summary
A technique for implementing a clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.