LC Frequency Synthesizer Startup With Adjustable FREF Delays
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Solution Overview
Problem
Frequency synthesizer implementations in IR-UWB radios face challenges due to long startup times and unpredictable phase alignment in LC oscillators, which affect power consumption and efficiency.
Innovation Solution
A frequency synthesizer system using an LC tank oscillator with a digital-to-time converter and phase detector, enabling duty-cycled operation and fractional frequency generation, allowing for fast startup and precise phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If LC oscillators are used for frequency synthesis, then frequency accuracy can be improved, but startup time becomes excessively long and phase alignment becomes unpredictable
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitor in the LC oscillator before enabling oscillation. The capacitor is charged to a specific voltage level (e.g., VDD/2) in advance, so when the oscillator is enabled, it can start immediately with a known initial condition, eliminating the long random startup time and unpredictable phase alignment of traditional LC oscillators
2Use of energy by moving object
If duty-cycled operation is implemented to reduce power consumption, then energy efficiency improves, but oscillator startup time and phase accuracy become critical constraints
Solution Approach 1:
The patent combines duty-cycled operation with preliminary action by pre-charging the capacitor during the inactive phase before each burst. This allows the oscillator to maintain low power consumption during idle periods while ensuring fast, deterministic startup when activated, because the capacitor is already charged to the correct voltage level and the oscillator can start immediately with a known phase
Solution Approach 2:
The patent implements periodic action through duty-cycled operation where the oscillator is activated only during burst periods and remains inactive during idle periods. This periodic activation pattern reduces average power consumption while the pre-charging mechanism ensures that each activation results in fast, predictable startup
3Loss of time
If ring oscillators are used to achieve fast startup, then startup time is reduced, but phase alignment accuracy and frequency precision are compromised
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitor to a specific voltage level (e.g., VDD/2) before enabling oscillation. This provides a deterministic initial condition that establishes a known phase relationship with the reference clock, achieving both fast startup and accurate phase alignment, unlike ring oscillators which have unpredictable startup phases
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system achieves low power consumption and efficient frequency synthesis with fast startup and accurate phase alignment, addressing the inefficiencies of traditional LC oscillators.
Implementation Method 1
an inductive-capacitive (LC) tank oscillator circuit configured to generate the RF signal
Implementation Method 2
A digital to time converter (DTC) circuit is configured to operate, for a first edge of the FREF clock, in a baseline mode that introduces a first delay value to the FREF clock
Implementation Method 3
A phase detector circuit is configured to detect, for the subsequent edges of the FREF clock and with the delay of the DTC circuit, a phase difference between the FREF clock and the RF signal
Data Source
AI summary
A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.