LC Frequency Synthesizer Startup With Adjustable Delay Phase Alignment

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Solution Overview

Problem

Existing frequency synthesizer implementations for IR-UWB radios face challenges in achieving low power consumption and fast startup times, particularly with LC oscillators having long startup times and random phase settings, which hinder efficient duty-cycled operations.

Innovation Solution

A frequency synthesizer system utilizing an LC tank oscillator circuit with a digital-to-time converter and controller circuit to introduce programmable delays, enabling duty-cycled operation and phase alignment, and incorporating a phase detector for phase difference detection, along with amplitude calibration mechanisms to maintain constant oscillation amplitude across a wide frequency range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If LC oscillators are used for frequency synthesis, then frequency accuracy is improved, but startup time becomes excessively long and startup phase is random

Engineering Contradiction:
Improvefrequency accuracyVSAvoidstartup time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-charging the capacitive element of the LC oscillator to a specific voltage level before activation. This pre-conditioning of the oscillator state enables immediate frequency accuracy upon activation while eliminating the random startup phase problem, as the oscillator begins from a known initial condition rather than from zero or random state.

Inventive Principle:
Principle #10Preliminary action

2Use of energy by moving object

If duty-cycled operation is implemented to reduce power consumption, then energy efficiency is improved, but phase alignment and startup accuracy become critical challenges

Engineering Contradiction:
Improvepower consumptionVSAvoidphase alignment accuracy
Core Design Contradiction:
Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by pre-charging the capacitive element to a specific voltage that corresponds to a known phase state before the duty-cycled activation. This ensures that when the oscillator is reactivated after being off, it starts with a predetermined phase alignment rather than a random phase, thereby maintaining phase synchronization while enabling power-saving duty-cycled operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies parameter changes by dynamically adjusting the pre-charge voltage level of the capacitive element based on the desired output frequency and phase requirements. By varying this voltage parameter, the system can achieve both power reduction through duty-cycling and precise phase alignment for different operating conditions.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If ring oscillators are used to achieve fast startup, then startup time is improved, but phase accuracy and frequency precision are lost

Engineering Contradiction:
Improvestartup timeVSAvoidphase accuracy
Core Design Contradiction:
Loss of timeVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary mechanism - a controlled pre-charge circuit with adjustable voltage - that bridges the gap between fast startup requirements and phase accuracy needs. This intermediary pre-conditions the LC oscillator to start quickly from a known phase state, combining the advantages of both ring and LC oscillators while eliminating their respective disadvantages.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP3136604B1Frequency synthesizers with adjustable delays
Publication Date: 2020.05.27 NXP BV
  • EP3136604B1 patent drawingFigure 1
  • EP3136604B1 patent drawingFigure 2
  • EP3136604B1 patent drawingFigure 3A

AI summary

A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.