Resonant LC Tank Package with Dielectric Spacer
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Solution Overview
Problem
Conventional CMOS inductors integrated with low-k dielectric layers over p-doped silicon substrates suffer from low Q-factors due to magnetic and capacitive coupling with the substrate, making them unsuitable for high Q-factor applications.
Innovation Solution
The solution involves fabricating an LC package with an inductor on low-k dielectric layers and a capacitor on high-k dielectric layers, positioning the capacitor between the inductor and the substrate, and using dielectric spacers to increase the distance between the inductor and the substrate, thereby reducing coupling and enhancing Q-factor and resonant frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If inductors are fabricated close to the low resistive substrate to reduce area, then area is reduced, but magnetic and capacitive coupling increases causing low Q-factor
Solution Approach 1:
A capacitor is introduced as an intermediary element positioned between the inductor and the substrate. This capacitor serves as a mediator that blocks magnetic and capacitive coupling paths while allowing the inductor to remain close to the substrate for area efficiency. The capacitor's dielectric structure acts as a barrier that prevents energy dissipation into the substrate while maintaining the compact layout.
Solution Approach 2:
The structure employs a nested arrangement where the capacitor is positioned within the vertical space between the inductor and the substrate. This nesting allows three components (inductor, capacitor, substrate) to occupy a compact vertical stack, achieving area reduction while maintaining proper electromagnetic isolation through the capacitor's positioning.
2Area of stationary object
If inductors are placed close to the substrate, then area is reduced, but energy dissipates in the substrate reducing resonant frequency
Solution Approach 1:
The capacitor acts as an intermediary that blocks the energy dissipation path into the substrate. By positioning the capacitor between the inductor and substrate, it creates an energy barrier that reflects or absorbs stray electromagnetic fields, preventing energy loss in the substrate while maintaining compact area.
Solution Approach 2:
The solution moves from a planar 2D layout to a 3D vertical stacking arrangement. By utilizing the vertical dimension to position the capacitor between the inductor and substrate, the design achieves area reduction in the horizontal plane while creating electromagnetic isolation in the vertical dimension, thus reducing energy dissipation.
3Ease of manufacture
If conventional CMOS processes are used, then manufacturing is simplified, but Q-factor remains low due to substrate coupling
Solution Approach 1:
The capacitor structure serves multiple functions: it acts as an electromagnetic isolation barrier, a decoupling element, and an integral part of the LC tank circuit. This multi-functionality allows a single component to address both the Q-factor improvement and the resonant frequency stabilization without requiring separate isolation structures, maintaining manufacturing simplicity.
Solution Approach 2:
The isolation and decoupling functions are merged into the capacitor structure itself. Rather than adding separate isolation layers or structures, the capacitor's dielectric and electrode configuration inherently provides both the capacitive function and the electromagnetic isolation, simplifying the overall manufacturing process while improving performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly increases the Q-factor and resonant frequency of the inductor, reducing noise-to-signal power ratio and enabling the creation of low-power phase lock-loops and wireless transceivers.
Implementation Method 1
magnetic and capacitive coupling between the inductor and the low resistive substrate
Implementation Method 2
magnetic and capacitive coupling between the inductor and the low resistive substrate
Implementation Method 3
high quality factors ("Q-factor") (e.g. greater than 30) inductors and capacitors having low phase noise
Data Source
AI summary
A package on a die having a low resistive substrate, wherein the package comprises an inductor on low-k dielectric and a capacitor on high-k dielectric. The stacked arrangement having different dielectric materials may provide an inductor having a high Q-factor while still having a high capacitance density. In addition, moving the inductor from the die to the package and fabricating the high density capacitor on the package reduces the silicon area required permitting smaller RF/analog blocks on the chip.