LC VCO and CML Divider Architecture for Low-Power High-Frequency Scaling
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Solution Overview
Problem
High-speed digital frequency dividers face challenges in power efficiency and compact circuit design, particularly at high radio operation frequencies, leading to increased power consumption and noise degradation, especially in low-powered mobile applications, and occupy large IC circuit areas due to the use of inductors and capacitor banks.
Innovation Solution
An integrated circuit comprising a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider, where the bias circuit generates bias voltages for the LC resonator and CML frequency divider, allowing the CML frequency divider to determine an output frequency based on the oscillation signal's AC and DC components, reducing circuit area and power consumption by utilizing a differential architecture and PMOS cross-coupled transistors for improved noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If digital frequency dividers are used for high-speed data transmission, then frequency synthesis and conversion functions are achieved, but power consumption increases significantly
Solution Approach 1:
The patent replaces traditional digital frequency divider circuits with an analog-based solution using an LC resonator circuit and CML frequency divider. This substitution transitions from purely digital logic operations to a hybrid analog-digital approach, where the LC resonator generates oscillation signals and the CML divider processes them, thereby reducing power consumption while maintaining high-speed operation capability.
Solution Approach 2:
The patent utilizes voltage-controlled oscillation frequency and current mode logic levels to optimize power consumption. By adjusting the control voltage applied to the LC resonator, the oscillation frequency can be tuned without significantly increasing power consumption, unlike traditional digital dividers that require full logic switching levels for frequency synthesis operations.
2Speed
If inductors and capacitor banks are used in voltage controlled oscillators, then high-frequency oscillation signals are generated, but circuit area increases
Solution Approach 1:
The patent employs differential architecture in the CML frequency divider and LC resonator circuit, where complementary PMOS and NMOS transistors are used in cross-coupled configurations. This local differentiation allows the circuit to achieve high-frequency oscillation with reduced component sizes, as the differential structure provides signal regeneration and noise rejection without requiring large inductor values or capacitor banks.
Solution Approach 2:
The patent transitions from single-ended circuit topology to differential topology, effectively adding a dimensional aspect to the signal processing. The differential pairs and cross-coupled structures operate in two complementary signal paths, allowing the circuit to achieve the same frequency multiplication function with smaller physical components by utilizing the voltage differential rather than absolute voltage levels.
3Productivity
If high-speed digital dividers are used, then frequency division is achieved, but noise degradation increases
Solution Approach 1:
The patent introduces an LC resonator circuit as an intermediary between the phase detector and the CML frequency divider. This resonator acts as a noise-filtering intermediary that selects the desired frequency component while attenuating noise and spurious signals. The resonator's high Q-factor provides natural frequency selectivity, reducing noise degradation before the signal reaches the digital frequency divider stage.
Solution Approach 2:
The patent replaces noisy digital logic-based frequency division with an analog-resonant approach using the LC resonator. The resonant circuit provides frequency selection and signal conditioning in the analog domain, avoiding the generation of digital switching noise that would occur in purely digital frequency division circuits operating at high speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves better power efficiency and compact circuit dimensions, reducing manufacturing costs and noise degradation while maintaining robustness over process variations, effectively addressing the limitations of traditional high-speed digital dividers.
Implementation Method 1
Voltage controlled oscillators typically utilize inductors and capacitor banks to form a resonance network, and generate high-frequency oscillation signals.
Data Source
AI summary
An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency.