LCCD Connectivity Representation for IC Physical Synthesis
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Solution Overview
Problem
Current electronic design automation systems for integrated circuits face inefficiencies in processing complex designs due to high network complexity and execution times, particularly in converting register transfer level (RTL) descriptions to physical layouts, as existing connectivity representations either lack explicit connectivity or are overly complex.
Innovation Solution
The method introduces a Lowest Common Connectivity Denominator (LCCD) representation that decomposes multi-bit buses into subsets sharing common patterns, reducing network complexity while maintaining compactness, by generating LCCD nets and pins that capture explicit connectivity, enabling efficient physical synthesis and layout optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bus level representation is used, then compactness is maintained, but explicit connectivity is lost making traversal inefficient
Solution Approach 1:
The bus level representation is segmented into bus-level objects (multi-bit nets and pins) that explicitly track connectivity relationships. Each bus-level object maintains references to its constituent bit-level elements, creating a hierarchical structure that preserves connectivity information while operating at the more compact bus level.
2Loss of information
If bit level representation is used, then explicit connectivity is captured, but network complexity increases significantly
Solution Approach 1:
Multiple bit-level nets and pins that share common connectivity patterns are merged into single bus-level objects. The bus-level representation combines multiple 1-bit connections into unified multi-bit nets, reducing the total number of objects in the network while maintaining explicit connectivity tracking through the hierarchical structure.
3Speed
If bit level representation is used, then traversal efficiency improves, but the representation becomes complex and incomprehensible to designers
Solution Approach 1:
The representation adds a hierarchical dimension by introducing bus-level objects that operate above the bit level. This creates a two-level hierarchy where bus-level objects provide designer-friendly abstractions for high-level navigation and understanding, while bit-level objects remain available for detailed traversal when needed.
Data Source
AI summary
A method for the abstraction of connectivity that provides an intermediate data path representation of integrated circuit (IC) designs is provided. The connectivity abstraction maintains the compactness of a bus level representation as well as the uniqueness of a bit level representation. Connectivity abstraction significantly reduces network complexity, i.e., the number of wires in a design and the execution time of physical synthesis of IC designs.