Analog Buffer Circuit for LCD Using Capacitor Reset and Feedback Control
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Solution Overview
Problem
Existing analog buffer circuits for LCD devices face issues with high power consumption and unstable data output due to standby current and oscillation, requiring additional components like D/A converters and amplifiers, which complicates luminance control and reduces reliability.
Innovation Solution
An analog buffer circuit design featuring a series connection of capacitors and inverters with reset and feedback switches, allowing for stable operation by storing and outputting voltage differences through capacitors, reducing power consumption and eliminating oscillation, while enabling capacitance ratio control for analog output voltage adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing analog buffer circuits are used in LCD devices, then data output can be provided, but power consumption is high and oscillation occurs reducing stability
Solution Approach 1:
The patent changes the circuit configuration parameters by using capacitors connected to fixed voltage nodes (VDD and VSS) instead of traditional amplifier circuits. This parameter change eliminates standby current while maintaining buffer functionality, resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The patent extracts and removes the problematic amplifier components and D/A converters from the circuit. By taking out these power-consuming elements and replacing them with a simplified capacitor-based voltage storage and transfer mechanism, the circuit achieves low power consumption while maintaining output stability.
2Adaptability or versatility
If additional components like D/A converters and amplifiers are added for luminance control, then luminance control capability is improved, but device complexity increases
Solution Approach 1:
The patent makes the capacitor-based circuit perform multiple functions: voltage storage, voltage difference transfer, and luminance control. By making the same circuit elements serve multiple purposes, the patent achieves adaptability without adding complexity, resolving the contradiction between versatility and device complexity.
Solution Approach 2:
The patent merges the functions of D/A converters, amplifiers, and buffer circuits into a single integrated capacitor-based voltage transfer mechanism. This consolidation eliminates the need for separate components while maintaining luminance control capability, thereby reducing overall circuit complexity.
3Ease of operation
If standby current flows in existing buffer circuits, then circuit operation is maintained, but power consumption increases
Solution Approach 1:
The patent uses periodic control signals (first control signal and second control signal) to selectively activate the capacitors for voltage storage and transfer operations. During non-active periods, the capacitors hold voltage without drawing standby current, thus eliminating continuous energy loss while maintaining operational capability when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed circuit achieves reduced power consumption and stable operation with minimized oscillation, allowing for precise control of analog output voltage and simultaneous digital-to-analog conversion, enhancing the reliability of the LCD device's data driver.
Implementation Method 1
a first capacitor and an inverter connected in series between an input terminal and an output terminal, a first reset switch connected between the input terminal and the first capacitor to reset the first capacitor
Implementation Method 2
a first capacitor and an inverter connected in series between an input terminal and an output terminal
Data Source
AI summary
An analog buffer circuit for a liquid crystal display (LCD) device includes a first capacitor and an inverter connected in series between an input terminal and an output terminal, a first reset switch connected between the input terminal and the first capacitor to reset the first capacitor, a first feedback switch connected to a first node between the first capacitor and the first reset switch, a second capacitor and a second feedback switch connected in series between a second node and a third node, the second node connected between the first capacitor and the inverter, and the third node connected between the inverter and the output terminal, a second reset switch connected between the second node and the third node to reset the inverter, and a third reset switch connected to a fourth node between the second capacitor and the second feedback switch to reset the second capacitor.