LCD Array Substrate Connecting Switches for Feed-Through Voltage
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Solution Overview
Problem
Conventional LCD technologies face issues with feed-through voltage, leading to brightness differences and image sticking due to limited capacitance in the pixel electrodes, which affects display quality.
Innovation Solution
Incorporating a connecting switch, specifically a second thin-film transistor, that electrically connects and disconnects pixel electrodes across adjacent rows and columns to increase overall capacitance, thereby reducing feed-through voltage and mitigating image sticking risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage capacitor Cst is increased to reduce feed-through voltage, then the feed-through voltage decreases, but the aperture ratio is limited and cannot be made larger
Solution Approach 1:
The patent merges the storage capacitor function with the liquid crystal capacitor by electrically connecting pixel electrodes of adjacent pixel units through connecting switches. This combines the capacitance of multiple pixel electrodes (Ctotal = Cgs + Cst + Clc + Cadditional) to achieve larger total capacitance without increasing the physical area of individual capacitors, thereby reducing feed-through voltage while maintaining aperture ratio.
Solution Approach 2:
The patent extends the capacitance accumulation from a single pixel unit to multiple pixel units in the row direction. By connecting pixel electrodes of adjacent pixel units (n-1, n, n+1) through connecting switches, the system accumulates capacitance across spatial dimensions, effectively increasing total capacitance without confining it to a single pixel area.
2Reliability
If the parasitic capacitor Cgs is reduced to reduce feed-through voltage, then the feed-through voltage decreases, but the pixel electrode capacitance is limited
Solution Approach 1:
The patent combines the capacitance of multiple pixel electrodes from adjacent pixel units to compensate for the limited parasitic capacitor. By electrically connecting pixel electrodes Pn-1, Pn, and Pn+1 through connecting switches Kn-1 and Kn, the system achieves larger total capacitance (Ctotal = Cgs + Cst + Clc + Cadditional) without needing to increase the parasitic capacitor of individual pixels.
3Reliability
If connecting switches are added to increase capacitance, then the feed-through voltage is reduced, but the device complexity increases
Solution Approach 1:
The connecting switches Kn-1 and Kn serve multiple functions: they act as storage capacitors by maintaining voltage on pixel electrodes, and they function as switches controlled by gate lines to connect or disconnect adjacent pixel units. This multi-functionality reduces the need for separate dedicated storage capacitors, thereby limiting the increase in device complexity.
Solution Approach 2:
The connecting switches are dynamically controlled by gate line voltages (Vgn-1 and Vgn) to connect or disconnect pixel electrodes as needed. During the charging period, the switches are on to allow capacitance accumulation; during the holding period, they are off to maintain the stored voltage. This dynamic control enables the system to adapt its configuration based on operational requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased capacitance effectively reduces feed-through voltage and minimizes image sticking, enhancing display quality by ensuring consistent charging across pixel units.
Implementation Method 1
Due to a voltage coupling effect of the thin-film transistors, at the moment when an electric potential of a gate signal decreases from a high level, a pixel charging voltage will have a change of a voltage difference ΔV
Data Source
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AI summary
An LCD array substrate, an LCD panel, and an LCD pixel circuit. The LCD array substrate comprises: a substrate, a plurality of gate lines (Gn, Gn+1, Gn+3 ...) and data lines (Dn, Dn+1, Dn+3 ...) formed on the substrate. The gate lines (Gn, Gn+1, Gn+3 ...) and the data lines (Dn, Dn+1, Dn+3 ...) intersect to form a plurality of pixel units (n, n+1 ...); a pixel electrode (Pn) and a first thin film transistor (Tn) are formed in each pixel unit (n). The pixel electrode (Pn) further comprises a connection switch (Kn) controlled by the gate lines (Gn, Gn+1, Gn+3 ...); the connection switch (Kn) is disposed between a pixel electrode (Pn-1) of a pixel unit (n-1) located in the same column and the previous row of the pixel unit (n) and a pixel electrode (Pn+1) of a pixel unit (n+1) located in the same column and the next row of the pixel unit (n).