LCD Array Substrate Four-Mask Process and Gate Opening Contact
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Solution Overview
Problem
The existing array substrate fabrication processes for liquid crystal display (LCD) devices face issues such as increased production costs, photo-current leakage, wavy noise, and reduced aperture ratio due to the use of multiple mask processes, which affect the quality of the displayed images.
Innovation Solution
The array substrate is fabricated using a four-mask process with a gate line, gate electrode, gate insulating layer, active layer, source and drain electrodes, and a passivation layer, where the pixel electrode contacts the drain electrode through a gate opening, preventing photo-current leakage and wavy noise, and maintaining an optimal aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask processes are used in array substrate fabrication, then manufacturing precision can be improved, but device complexity and production costs increase
Solution Approach 1:
The patent combines multiple mask processes into a single integrated mask process. The method forms the gate electrode, active layer, source/drain electrodes, and pixel electrode pattern simultaneously using one mask, eliminating the need for separate masking steps for each layer. This merging approach maintains fabrication precision while significantly reducing process complexity and production costs.
Solution Approach 2:
The single mask used in the invention serves multiple functions: it defines the gate electrode pattern, the active layer pattern, the source and drain electrode patterns, and the pixel electrode pattern all in one step. This multi-functional mask design allows the same masking structure to control multiple critical features, reducing the total number of mask processes required.
2Manufacturing precision
If multiple mask processes are used in array substrate fabrication, then manufacturing precision can be improved, but production costs increase
Solution Approach 1:
The patent combines multiple mask processes into a single integrated mask process. The method forms the gate electrode, active layer, source/drain electrodes, and pixel electrode pattern simultaneously using one mask, eliminating the need for separate masking steps for each layer. This merging approach maintains fabrication precision while significantly reducing process complexity and production costs.
3Reliability
If the pixel electrode is isolated from the drain electrode, then electrical insulation is improved, but photo-current leakage increases
Solution Approach 1:
The patent extracts the gate insulating layer in the gate opening region to create a direct contact path between the pixel electrode and drain electrode. By removing the insulating barrier in this specific location, the design allows the pixel electrode to contact the drain electrode directly, preventing photo-current leakage while maintaining electrical insulation in other regions where the gate insulating layer remains intact.
4Illumination intensity
If the aperture ratio is increased, then display quality is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent combines multiple mask processes into a single integrated mask process. The method forms the gate electrode, active layer, source/drain electrodes, and pixel electrode pattern simultaneously using one mask, eliminating the need for separate masking steps for each layer. This merging approach maintains fabrication precision while significantly reducing process complexity and production costs.
Data Source
AI summary
An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode and including a gate opening; an active layer on the gate insulating layer and overlapping the gate electrode; an ohmic contact layer on the active layer; a source electrode on the ohmic contact layer; a drain electrode on the ohmic contact layer and spaced apart from the source electrode, wherein one end of the drain electrode is disposed in the gate opening; a data line on the gate insulating layer and connected to the source electrode, the data line crossing the gate line; a passivation layer on the data line and the source and drain electrodes and including a pixel opening, wherein the pixel opening exposes the drain electrode in the gate opening and a portion of the gate insulating layer; and a pixel electrode on the gate insulating layer and in the pixel opening, the pixel electrode contacting the one end of the drain electrode in the gate opening.