LCD Array Substrate Without Passivation Layer
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Solution Overview
Problem
The existing array substrate fabrication for LCDs requires multiple masking processes, leading to increased fabrication time, cost, and risk of substrate failures due to the need for a passivation layer and complex photolithography steps, which can result in reduced picture quality and storage capacitance issues.
Innovation Solution
A method and structure for an array substrate that eliminates the passivation layer, reducing the number of masking processes by directly connecting the pixel electrode to the drain electrode without a passivation layer, using a diffraction mask to form the necessary patterns with fewer equipment requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a passivation layer is formed to protect the TFT structure, then the reliability of the device is improved, but the fabrication complexity and number of masking processes increases
Solution Approach 1:
The patent extracts and removes the passivation layer from the conventional TFT structure. By eliminating this layer, the patent reduces the number of masking processes from five or six to three, while maintaining device reliability through alternative protective measures integrated into the gate structure.
Solution Approach 2:
The patent merges the protective function previously provided by the passivation layer into the gate insulating layer structure. The gate insulating layer is designed to serve both as an electrical insulator and as a protective barrier, combining multiple functions into a single integrated structure.
2Manufacturing precision
If multiple masking processes are used for photolithography, then the manufacturing precision is improved, but the fabrication time and cost increase
Solution Approach 1:
The patent combines multiple patterning functions into fewer masking steps. By redesigning the gate structure with integrated protective features, the patent achieves the same patterning precision with only three masking processes instead of five or six, significantly reducing fabrication time.
Solution Approach 2:
The patent performs preliminary structuring of the gate insulating layer to pre-establish protective barriers and patterning features. This preliminary action eliminates the need for subsequent passivation layer deposition and related masking steps, reducing overall fabrication time while maintaining precision.
3Reliability
If a passivation layer with contact holes is formed, then the electrical connections are protected, but the fabrication cost and equipment requirements increase
Solution Approach 1:
The patent extracts and eliminates the separate passivation layer and its associated contact hole formation processes. Electrical connections are protected through the integrated gate insulating layer structure, removing the need for costly plasma-enhanced chemical vapor deposition equipment and reducing fabrication costs.
Solution Approach 2:
The gate insulating layer is designed to serve multiple functions simultaneously: electrical insulation, mechanical protection, and contact hole formation. This multi-functionality eliminates the need for separate passivation layer processes, reducing equipment requirements and fabrication costs.
4Manufacturing precision
If five or six masks are used for fabricating the array substrate, then the manufacturing precision is maintained, but the productivity decreases
Solution Approach 1:
The patent merges the functions of five or six separate masks into three integrated masking steps. By consolidating the gate structure design to include protective features and patterning elements, the patent maintains substrate patterning precision while doubling fabrication throughput.
Solution Approach 2:
The patent segments the fabrication process into three distinct masking stages, each performing multiple functions. This segmentation reduces the total number of steps while maintaining precision by focusing each mask on specific critical patterning operations.
Data Source
AI summary
Disclosed is an array substrate of an LCD, and a method for fabricating it, which simplifies the fabrication process, thereby reducing fabrication costs. The process is simplified because the array substrate does not have a passivation film. The thin film transistors on the array substrate each have an active layer that is protected from contamination by forming a channel insulation layer on the active layer through a dry-etching process. Further, the gate line, gate pad, and gate electrode may have a two-layer structure having a low-resistance metal layer and a barrier metal layer, or a three-layer structure having a low-resistance metal layer and two barrier metal layers.