Backlight Driver Synchronization Circuit for LCD Flicker Control
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Solution Overview
Problem
Conventional backlight drivers for liquid crystal display devices face difficulties in synchronizing input and output synchronization signals due to sudden frequency changes, leading to brightness fluctuations and flickering issues.
Innovation Solution
A method and circuit that synchronize input and output synchronization signals by setting the output period based on a comparison between the input period and the previous output period, while limiting the output period within a predefined range to stabilize internal clocks and prevent sudden changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the output period is set based on sudden frequency change of input VSYNC signal, then the backlight driver responds to frequency change, but the output period deviates from desired value causing brightness fluctuation and flickering
Solution Approach 1:
The patent implements dynamic period adjustment by comparing input VSYNC period with previous output period and calculating difference values. The system dynamically adapts the output period based on detected frequency changes while maintaining stability through controlled adjustment steps and accumulation mechanisms that prevent sudden deviations.
Solution Approach 2:
The patent employs feedback mechanisms by continuously monitoring the input VSYNC signal period, comparing it with the previous output period, and using the difference value to adjust subsequent output periods. This closed-loop feedback ensures the output period adapts to frequency changes while maintaining brightness stability.
2Measurement precision
If the output period is calculated on a per frame basis, then the system tracks frequency changes, but sudden frequency changes cause the backlight driver to fail to set output period properly
Solution Approach 1:
The patent applies beforehand cushioning by accumulating difference values over multiple frames and using threshold comparisons before applying period adjustments. This prevents sudden frequency changes from immediately disrupting the output period, providing a buffer that ensures reliable period setting even during frequency transitions.
Solution Approach 2:
The patent performs preliminary actions by detecting and accumulating period differences in advance before finalizing output period settings. The system prepares adjustment values through accumulation and threshold validation, ensuring that frequency tracking remains precise while period setting remains reliable during sudden changes.
3Adaptability or versatility
If the PWM duty ratio is generated using suddenly changed input period, then the system responds to frequency变化, but the duty ratio deviates from desired value causing image quality deterioration
Solution Approach 1:
The patent implements dynamic duty ratio generation by continuously adjusting the PWM duty cycle based on accumulated period differences and threshold comparisons. This dynamic adjustment mechanism allows the system to adapt to frequency changes while maintaining precise duty ratio control, preventing image quality deterioration.
Solution Approach 2:
The patent uses feedback control in the PWM generation process by monitoring period differences and adjusting duty ratios accordingly. The accumulated difference values feed back into the duty cycle calculation, ensuring that the PWM signal maintains accurate duty ratios even during frequency transitions, thereby preserving image quality.
Data Source
AI summary
Disclosed are method and circuit for synchronizing input and output synchronization signals, which can synchronize an output synchronization signal based on frequency change of an input synchronization signal and limit input and output periods, thereby preventing flickering, a backlight driver of a liquid crystal display device using the same, and a method for driving the backlight driver. The method for synchronizing input and output synchronization signals, includes generating an output synchronization signal whose output period is set based on a comparison result between an input period of an input synchronization signal and a previous output period of the output synchronization signal, and limiting the output period of the output synchronization signal within a predefined limit range from the previous output period.