LCD Array Substrate Barrier Patterns for Channel Width Control
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Solution Overview
Problem
The existing methods for fabricating array substrates for LCD devices often result in variations of the channel region width due to over-etching during the wet-etching process, leading to degraded properties of the thin film transistor (TFT) and signal delay issues, particularly in in-plane switching (IPS) mode.
Innovation Solution
The implementation of barrier patterns formed by anisotropic dry-etching under the source and drain electrodes, which are not reactive with the etchant, ensures that the channel region maintains the desired critical dimension, thereby preventing width variations and improving TFT properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wet-etching process is used to form source and drain electrodes, then the etching process is simple and fast, but the channel region width varies due to over-etching
Solution Approach 1:
A barrier pattern is introduced as an intermediary layer between the source/drain electrodes and the channel region. This barrier pattern acts as a protective mediator that prevents the etchant from directly contacting and over-etching the channel region, while still allowing the wet-etching process to efficiently form the source and drain electrodes.
Solution Approach 2:
The barrier pattern is formed in advance before the source and drain electrodes are created. This preliminary action establishes a protective structure that will prevent over-etching of the channel region during the subsequent electrode formation process, ensuring precise channel width control from the outset.
2Reliability
If the channel region width is reduced to improve TFT properties, then the TFT performance improves, but signal delay increases in IPS mode
Solution Approach 1:
The invention changes the geometric parameters of the barrier pattern (width, position, shape) to optimize the channel region dimensions. By carefully controlling these parameters, the channel width is reduced to improve TFT properties while maintaining sufficient signal transmission speed for IPS mode operation.
3Manufacturing precision
If barrier patterns are added to prevent over-etching, then channel region width control improves, but device complexity increases
Solution Approach 1:
The barrier pattern is applied locally only where needed - specifically at the boundaries of the channel region where over-etching would occur. This localized approach provides precise width control at critical areas without adding unnecessary complexity to the entire device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that the channel region width corresponds to the desired critical dimension, reducing TFT property degradation and minimizing signal delay issues, even when the source and drain electrodes are over-etched, and can be applied to both standard and IPS mode LCD devices.
Implementation Method 1
The implementation of barrier patterns formed by anisotropic dry-etching under the source and drain electrodes
Data Source
AI summary
An array substrate for a liquid crystal display device includes a gate line on a substrate; a gate insulating layer on the gate line; a data line crossing the gate line; a gate electrode connected to the gate line; an active layer on the gate insulating layer and overlapping the gate electrode; first and second ohmic contact layers on the active layer, the first and second ohmic contact layers spaced apart from each other by a first distance; first and second barrier patterns spaced apart from each other by the first distance and on the first and second ohmic contact layers, respectively. The active layer is exposed through the first and second barrier patterns; source and drain electrodes spaced apart from each other by a second distance greater than the first distance and on the first and second barrier patterns, respectively.