LCD Bezel Reduction via Source Lead-out Line Routing
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Solution Overview
Problem
Conventional LCD devices face challenges in reducing bezel size while maintaining pixel aspect ratio due to the arrangement of source and gate lines, which affects the aperture ratio and space for pixel driving components.
Innovation Solution
The implementation involves arranging source lead-out lines and gate lines in a manner that allows them to overlap or extend along regions of the sub-pixel electrodes that do not contribute to the aspect ratio, enabling a reduction in bezel size without compromising the pixel aspect ratio by isolating and strategically placing these lines within the LCD panel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If source and gate lines are arranged in conventional LCD devices, then the pixel aspect ratio can be maintained, but the bezel size cannot be reduced due to space requirements for driving components
Solution Approach 1:
The source lead-out lines are routed to extend along the third region of sub-pixel electrodes (the region containing boundaries of slits) rather than being confined to traditional edge positions. This spatial reconfiguration in a different dimensional arrangement allows driving components to be positioned more efficiently, reducing bezel size while maintaining proper electrical connections to pixel elements.
Solution Approach 2:
The source lead-out lines are specifically positioned to overlap with the third region of sub-pixel electrodes, which contains the boundaries of slits and does not contribute to the aspect ratio. This localized placement strategy optimizes space utilization in specific regions without affecting the overall pixel aspect ratio, enabling bezel reduction.
2Length of stationary object
If source lead-out lines are positioned to reduce bezel size, then the bezel can be made smaller, but the arrangement becomes more complex
Solution Approach 1:
The source lead-out lines are merged with the third region of sub-pixel electrodes, where they extend along and overlap with the boundary regions of slits. This merging allows the lead-out lines to utilize existing structural spaces within the pixel electrode design, reducing the need for separate routing channels and simplifying the overall manufacturing process despite the optimized positioning.
3Area of stationary object
If source lead-out lines overlap with third region of sub-pixels, then space is optimized for driving components, but the manufacturing precision requirements increase
Solution Approach 1:
The third region of sub-pixel electrodes, which contains the boundaries of slits, is pre-defined during the pixel electrode fabrication process. By establishing this region in advance with clear geometric boundaries, the subsequent routing of source lead-out lines can be precisely aligned to this predetermined area, reducing the actual manufacturing precision requirements during the lead-out line formation stage.
Data Source
AI summary
Techniques of reducing bezel size of liquid crystal display (LCD) devices are described. Techniques of the present subject matter allow reduction in the bezel size of an LCD device while maintaining the aspect ratio of pixels of an LCD panel. In an example, an LCD panel of the LCD device may include a plurality of sub-pixels arranged in a first direction and a second direction in a matrix arrangement, and a plurality of gate lines extending in the first direction and a plurality of source lines extending in the second direction. Further, The LCD panel may include a plurality of source lead-out lines extending in the first direction, wherein each of the plurality of source lead-out lines is electrically connected to at least one of the plurality of source lines.