Bi-directional Gate Drive Circuit for LCD Data Line Reduction
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Solution Overview
Problem
Existing liquid crystal display (LCD) devices require a large number of data driver ICs, which contribute significantly to the material and production costs, and existing methods to reduce the number of data lines often necessitate additional gate driver ICs, limiting cost reduction and increasing complexity.
Innovation Solution
A bi-directional internal gate drive circuit is implemented, allowing one gate driving circuit to drive half of the LCD device independently of another, enabling data line sharing without increasing the gate driving speed or reducing effective pixel charging time, thus reducing the number of data lines and gate lines without the need for external drive ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of data lines is reduced by sharing data lines between pixels, then the number of data driver ICs is reduced, but the gate driving speed must be increased to maintain effective pixel charging time
Solution Approach 1:
The gate driver circuit is divided into multiple independent segments, each capable of driving a subset of gate lines. This segmentation allows parallel operation of multiple gate drivers, effectively increasing the overall gate driving speed without requiring individual pixels to be charged faster by a single gate driver. The segmentation enables the system to handle reduced data line counts while maintaining adequate charging time through concurrent operations.
2Quantity of substance
If additional gate driver ICs are added to enable data line sharing, then the number of data lines can be reduced, but the device complexity and production cost increase
Solution Approach 1:
Multiple gate driver circuits are merged into a unified architecture where they share common control signals and power supply networks. The gate drivers are designed to operate in a coordinated manner with synchronized timing, allowing them to function as an integrated system rather than separate independent units. This merging approach reduces overall device complexity while enabling data line sharing.
Solution Approach 2:
The gate driver circuit is designed with multi-functionality to perform both sequential scanning and parallel driving operations. The same gate driver infrastructure can adapt to different driving modes depending on the display requirements, eliminating the need for separate dedicated circuits for different functions. This universality reduces device complexity while maintaining the capability to reduce data line counts.
3Duration of action of moving object
If the gate driving speed is increased to compensate for reduced pixel charging time, then the pixel charging time is maintained, but the manufacturing precision and reliability decrease
Solution Approach 1:
The gate driver circuits are pre-configured with optimized timing parameters and voltage levels that are determined during the design phase. The charging sequences are planned in advance to ensure that each pixel receives the appropriate charge duration without requiring real-time speed adjustments. This preliminary action ensures manufacturing precision is maintained while achieving the required effective charging time.
Solution Approach 2:
The gate driving operation maintains continuous useful action by ensuring that pixel charging never interrupts or experiences gaps. The segmented gate drivers operate in a coordinated continuous sequence, transferring charge smoothly across all pixels without interruption. This continuity ensures both the required charging duration and manufacturing precision are maintained.
Data Source
AI summary
Disclosed herein are a liquid crystal display device, in which a bi-directional internal gate drive circuit is used to cut the number of data lines in half, and a method of driving such liquid crystal display devices. The liquid crystal device includes a pixel array having a plurality of pixels on a lower substrate. The pixels are configured such that two pixels horizontally adjacent to each other are paired to share the same data line. First and second gate drive circuits are housed in the left and right sides of the lower substrate so as to be independently operated in the left and right side of the pixel array. The first gate drive circuit is formed of first to nth odd shift registers, and the second gate drive circuit is formed of first to nth even shift registers.