LCD Chip Coupling Layout for Precision Bonding

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Solution Overview

Problem

Conventional chip bonding technologies face challenges in achieving precise electrical connections due to machine imprecision, leading to inadequate contact areas, potential short-circuits, and increased IC chip size, which hinders miniaturization and increases manufacturing costs.

Innovation Solution

A non-linear layout structure with shifting lines and adjustable conductive pads allows for improved tolerance against machine imprecision, preventing short-circuits and enabling miniaturization of the IC chip by optimizing the bonding area without requiring larger bumps or more precise machines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If adequate spacing is maintained between conductive pads and adjacent lines to prevent short-circuits, then reliability is improved, but the area of the IC chip increases

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidIC chip area
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent applies local quality by making the conductive pads asymmetric in shape, with extended portions that locally increase the contact area with bumps while maintaining compact overall layout. This allows adequate electrical connection reliability in critical areas without increasing the total IC chip area

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses dimensionality change by extending conductive pads in specific directions (creating asymmetric shapes with extended portions) rather than uniformly increasing pad size in all directions. This allows optimization of contact area in the critical bonding dimension while maintaining compact layout in other dimensions

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of moving object

If smaller spacing between lines and conductive pads is used to reduce product size, then the area of the IC chip decreases, but the risk of short-circuits increases due to machine imprecision

Engineering Contradiction:
ImproveIC chip areaVSAvoidelectrical connection reliability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The asymmetric conductive pad design with extended portions creates local quality variations that provide built-in tolerance for machine imprecision. The extended portions ensure adequate contact area even when positioning varies, allowing smaller overall spacing without increasing short-circuit risk

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The extended portions of the conductive pads act as a cushion against positioning errors. By designing the pads with extra extension in critical directions, the patent compensates for anticipated machine imprecision before bonding occurs, allowing tighter spacing without sacrificing reliability

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If larger conductive pads are used to ensure adequate contact area, then electrical conductivity is improved, but the area of the IC chip increases

Engineering Contradiction:
Improveelectrical conductivityVSAvoidIC chip area
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent applies local quality by creating asymmetric conductive pads with extended portions that locally increase contact area only where needed for electrical conductivity. This avoids uniformly enlarging pads in all directions, thereby maintaining compact IC chip area while ensuring adequate electrical connection

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8188607B2Layout structure for chip coupling
Publication Date: 2012.05.29 AU OPTRONICS CORP
  • US8188607B2 patent drawing
  • US8188607B2 patent drawing
  • US8188607B2 patent drawing

AI summary

A layout structure disposed on the substrate of the liquid crystal display (LCD) for chip coupling is provided. The first and second orientations that are substantially perpendicular to the first orientation can be defined on the substrate. The layout structure includes a plurality of lines, which extend along the second orientation, and a plurality of conductive pads that are respectively disposed on the lines. The conductive pads are distributed along the first orientation and staggered along the second orientation. Each line can shift away from the adjacent conductive pad on the first orientation. Thus, the LCD chip has a better conductivity and a thinner dimension under the precision of the conventional machines.