Liquid Crystal Display With Electrically Connected Gate Lines

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Solution Overview

Problem

Liquid crystal displays (LCDs) face challenges in achieving high-speed driving due to slow response times and increased parasitic capacitance, which affects image quality and vertical crosstalk, especially as display size and pixel count grow.

Innovation Solution

The LCD design includes electrically connected gate lines and data lines arranged in pairs with specific polarity configurations and overlapping structures to ensure sufficient charge time and prevent vertical crosstalk, using a matrix arrangement of pixels with switching elements and capacitors to optimize signal transmission and voltage application.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the number of gate lines is increased to support larger display sizes, then the display area increases, but the charge time for each pixel is shortened

Engineering Contradiction:
Improvedisplay areaVSAvoidcharge time
Core Design Contradiction:
Area of stationary objectVSLoss of time

Solution Approach 1:

The gate lines are divided into multiple groups, with each group sharing a common gate electrode. This segmentation allows the display to maintain a large number of horizontal scan lines while reducing the total number of independent gate electrodes needed, thereby preserving charge time despite increased display area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Adjacent gate lines are merged by sharing common gate electrodes. Multiple gate lines within each group receive the same gate signal simultaneously, which reduces the overall number of gate switching operations and ensures sufficient charge time is available even as the display size increases.

Inventive Principle:
Principle #5Merging (Combining)

2Measurement precision

If the number of pixels is increased to improve image resolution, then the image quality improves, but the parasitic capacitance increases

Engineering Contradiction:
Improveimage resolutionVSAvoidparasitic capacitance
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and separates the data transmission function into dedicated data lines that are distinct from the gate lines. By taking out the data signal path from the gate control path, the parasitic capacitance between gate lines and pixel electrodes is reduced, allowing for higher pixel counts without proportionally increasing harmful capacitance effects.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a temporal dimension to data transmission by using alternating polarity schemes and timed signal sequences. This dimensional approach allows data to be transmitted through shared lines at different times with different polarities, effectively managing parasitic capacitance effects while supporting high-resolution displays.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If the driving speed is increased to display moving images, then the motion display capability improves, but the vertical crosstalk increases

Engineering Contradiction:
Improvedriving speedVSAvoidvertical crosstalk
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent employs periodic alternating polarity schemes where data signals are transmitted with alternating positive and negative polarities across different time periods. This periodic action allows the system to achieve high driving speeds for motion display while the alternating polarities cancel out parasitic capacitance effects that would otherwise cause vertical crosstalk.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent changes the electrical parameters of the data signals by implementing alternating voltage polarities and timed signal levels. By dynamically changing these parameters in a periodic manner, the system achieves fast response times for moving images while the parameter variations compensate for and reduce vertical crosstalk caused by parasitic capacitance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration secures sufficient charge time for each pixel, reduces vertical crosstalk, and efficiently arranges signal lines, enhancing the display's ability to handle increased size and speed requirements while maintaining image quality.

Implementation Method 1

The field generating electrodes generate an electric field in the liquid crystal layer when a voltage is applied thereto, thus determining alignment of liquid crystal molecules of the liquid crystal layer and controlling polarization of incident light

Methodology Applied
Scientific EffectElectric field: Electric Field

Implementation Method 2

By controlling the polarization of incident light an LCD may also control the transmittance of that light to an outside

Methodology Applied
Scientific EffectPolarization: Polarisation

Implementation Method 3

Each pixel includes first and second liquid crystal capacitors, a first storage capacitor, and a second storage capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS8111366B2Liquid crystal display and method of driving the same
Publication Date: 2012.02.07 LONESTAR CRYSTAL DISPLAY LLC
  • US8111366B2 patent drawing
  • US8111366B2 patent drawing
  • US8111366B2 patent drawing

AI summary

A liquid crystal display includes; a first substrate, a plurality of pixels arranged substantially in a matrix-shape on the first substrate; a plurality of gate lines disposed on the first substrate and which transmit gate signals to the pixels, and a plurality of data lines which intersect the gate lines and which transmit data voltages to the pixels, wherein at least two adjacent gate lines are electrically connected to each other.