LCD Data Drive Circuit Alternating Buffer Patterns

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Solution Overview

Problem

Liquid crystal display devices suffer from poor picture quality due to offset errors in data buffering, causing inconsistent gray levels across vertical lines, which affect user perception.

Innovation Solution

A liquid crystal display device with a data drive circuit that realigns digital data patterns into analog voltages and buffers them according to sub-pixel arrangements, allowing for adaptive supply of analog data voltages to each pixel, thereby maintaining consistent gray levels across horizontal lines by alternating the buffering location for each horizontal period.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If analog data voltages are buffered in fixed output buffers for each vertical line, then data supply is simplified, but gray level inconsistencies and poor picture quality occur due to offset errors

Engineering Contradiction:
Improvedata supply structureVSAvoidgray level consistency
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies dynamics by making the data supply pattern changeable over time. Specifically, the data drive circuit alternates between different data supply patterns (first pattern and second pattern) for adjacent horizontal lines, allowing the system to adapt dynamically rather than using a fixed buffering structure. This temporal variation enables compensation for offset errors while maintaining a relatively simple hardware architecture.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action by alternating the data supply pattern for adjacent horizontal lines in a regular cycle. The data drive circuit switches between the first data supply pattern and the second data supply pattern periodically, with odd horizontal lines receiving one pattern and even horizontal lines receiving the other pattern. This periodic alternation averages out the offset errors over time, improving gray level consistency without requiring complex compensation circuits.

Inventive Principle:
Principle #19Periodic action

2Productivity

If data is supplied to each pixel through dedicated output buffers, then data transmission is efficient, but offset errors cause visual defects in picture quality

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidpicture quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent maintains efficient data transmission through dedicated output buffers while introducing dynamic pattern switching to compensate for offset errors. The data drive circuit uses multiple output buffers (first and second output buffers) that supply data in alternating patterns, allowing the system to maintain high data transmission efficiency while improving picture quality through temporal variation in the data supply approach.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent converts the harmful effect of offset errors in the output buffers into a beneficial averaging effect. By supplying data from different output buffers in alternating patterns to adjacent horizontal lines, the offset errors from different buffers are distributed and averaged across the display, transforming the previously harmful consistent offset into a beneficial randomization that improves overall gray level uniformity.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS8872742B2LCD and drive method thereof
Publication Date: 2014.10.28 LG DISPLAY CO LTD
  • US8872742B2 patent drawing
  • US8872742B2 patent drawing
  • US8872742B2 patent drawing

AI summary

This invention relates to a liquid crystal display device and its driving method for improving a visual picture quality. A liquid crystal display device according to an embodiment includes a liquid crystal display panel where plural pixels composed of sub-pixels arranged in a fixed pattern are arranged by the unit of one horizontal line; a timing controller for controlling the gray level realization of digital data inputted from a system; and a data drive circuit that differently realigns a data pattern of the digital data by the unit of one horizontal line for each k horizontal period, that converts the digital data of the realigned data pattern into analog data voltages, and that makes the analog data voltages, which are buffered in accord with the realigned data pattern, in accord with an arrangement pattern of the sub-pixels constituting each pixel to supply the analog data voltages to each pixel.