LCD Data Interface Multiplexing Reduces Routing Space
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Solution Overview
Problem
LCD display ICs face challenges in achieving high power efficiency, low production cost, and smaller size due to the large routing space and increased power consumption caused by the numerous transmission lines required for data access in existing data accessing systems.
Innovation Solution
A data accessing interface with a multiplex output module and a sequential input module is introduced, utilizing a buffer unit and multiplexers to reduce the number of transmission lines by selecting and outputting M-bit digital data from N-bit data stored in the memory, thereby minimizing memory array access and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each row of data in the memory is accessed and latched in respective latches of the buffer unit through transmission lines, then the digital data can be transmitted to the source device, but the number of transmission lines increases significantly, resulting in large routing space requirements
Solution Approach 1:
Multiple transmission lines are merged into a single shared transmission line through the use of multiplexers. The multiplex output module combines data from multiple latches and transmits them sequentially over one shared transmission line to the sequential input module, eliminating the need for separate transmission lines for each latch and significantly reducing routing space requirements.
Solution Approach 2:
The system dynamically switches between different data sources using multiplexers controlled by control signals. The multiplex output module dynamically selects which latch data to transmit at each clock cycle, and the sequential input module dynamically captures data from the shared transmission line at the appropriate timing, enabling flexible and efficient data routing with minimal physical connections.
2Productivity
If numerous transmission lines are used to transmit data between the buffer unit and the source device, then complete row data can be transmitted, but the total load of the transmission lines increases, raising the overall power consumption
Solution Approach 1:
Multiple high-power transmission lines are replaced by a single shared transmission line. By combining the data paths and using time-division multiplexing, the system transmits the same amount of data with significantly reduced total line load and lower overall power consumption, while maintaining complete data transmission capability.
Solution Approach 2:
The system uses periodic clock signals to control the sequential transmission of data through the multiplexers and latches. Data is transmitted in periodic cycles where the multiplex output module selects and transmits data from multiple latches sequentially, and the sequential input module captures the data at regular intervals, achieving efficient data transfer with reduced power consumption compared to simultaneous multi-line transmission.
3Reliability
If the buffer unit contains a large number of latches to store complete row data, then all pixel data can be buffered, but the device complexity and cost increase
Solution Approach 1:
The system merges the buffering function across multiple latches in the multiplex output module and the sequential input module. Instead of requiring all latches to simultaneously hold complete row data, the latches work together in a pipelined fashion where data is loaded into one module while being transmitted to and captured by the other module, reducing the total number of latches needed while maintaining full buffering capability.
Data Source
AI summary
A data accessing interface between memory and source in LCD display IC includes a multiplex output module and a sequential input module. Suppose a row width of the memory is N bit. The multiplex output module is for outputting a row N-bit digital data. The multiplex output module includes a buffer for receiving the row N-bit digital data from the memory; and a multiplex unit for continuously selecting M bits from the N bit digital data to output to source. After N/M times, all of the row N bit digital data will be output to source. The sequential input module includes N latches and N/M latch control signals; when each latch control signal is active, it will latch M bit digital data from the multiplex output into M latches. After N/M latch control signals are active sequentially, the N bit digital data are stored into the N latches for source.