Liquid Crystal Display Data Line Segmentation for Mura Reduction
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Solution Overview
Problem
Conventional liquid crystal displays with dual gate circuits reduce the number of data lines to lower costs but often compromise display quality due to electrical potential coupling between pixel electrodes, resulting in vertical mura.
Innovation Solution
The implementation of a liquid crystal display design where each data line is composed of two sub-data lines that connect to non-adjacent columns of pixels, with an additional column of pixels interposed between the connected columns, allowing for reduced data lines while maintaining display quality by canceling out capacitance coupling between adjacent pixel electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the number of data lines is decreased to lower cost, then manufacturing cost is reduced, but display quality deteriorates due to electrical potential coupling between pixel electrodes
Solution Approach 1:
Each data line is divided into two sub-data lines that connect to different columns of pixels. This segmentation allows the circuit to drive fewer physical data lines while maintaining the ability to address all pixel columns, thereby reducing manufacturing cost without compromising display quality. The sub-data lines are selectively activated based on which columns need updating, preventing electrical potential coupling issues.
Solution Approach 2:
The patent implements a dynamic driving method where the controller selectively activates different sub-data lines based on which columns of pixels require updating. This dynamic approach allows the system to use fewer physical data lines while maintaining full display functionality and quality, as only the necessary sub-data lines are activated at any given time, avoiding electrical potential disturbances.
2Device complexity
If each data line connects to adjacent columns of pixels to reduce the number of data lines, then device complexity is reduced, but electrical potential coupling occurs between pixel electrodes
Solution Approach 1:
The data lines are segmented into sub-data lines that connect to non-adjacent columns of pixels. Each sub-data line is responsible for specific columns, and by activating only the necessary sub-data lines, the system avoids electrical potential coupling between adjacent pixel electrodes while maintaining reduced device complexity.
Solution Approach 2:
The controller acts as an intermediary that selectively activates specific sub-data lines based on which columns need updating. This selective activation prevents electrical potential coupling by ensuring that only the necessary sub-data lines are active at any given time, thereby eliminating the harmful effect while maintaining the simplified data line structure.
3Manufacturing precision
If higher resolution is needed, then display quality is improved, but the number of data lines and data drivers must be increased resulting in higher cost
Solution Approach 1:
By segmenting each data line into two sub-data lines that connect to different columns, the system can achieve higher resolution displays without proportionally increasing the number of physical data lines. The selective activation of sub-data lines based on column update needs allows high-resolution display while controlling manufacturing cost.
Solution Approach 2:
The patent changes the driving parameters by selectively activating different sub-data lines based on which columns require updating. This parameter change approach allows the system to maintain high display resolution while using fewer physical data lines, thereby controlling manufacturing cost without sacrificing display quality.
Data Source
AI summary
An embodiment of this invention provides a liquid crystal display, which comprises a thin-film transistor substrate, an upper substrate, and a liquid crystal between the two substrates. The thin-film transistor substrate comprises data lines, gate lines, and a pixel array defined by the data lines and gate lines, characterized in that each data line connects to two columns of pixel, and another one or two columns of pixel are interposed between the connected two columns of pixel.


