LCD Discharging Circuit Using Single Capacitor Delay
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Solution Overview
Problem
Existing liquid crystal display devices require a complex and costly discharging circuit with multiple low-capacitance capacitors to delay the discharge of remaining charges, increasing fabrication costs and circuit complexity.
Innovation Solution
A liquid crystal display device and method that utilize a first and second pumping unit to generate a gate high voltage, a level shifter to adjust voltage levels, and a delay device with a single low-capacitance capacitor to maintain the gate high voltage for a preset period, reducing the number of delay devices needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple low-capacitance capacitors are used to maintain gate high voltage for discharging, then the discharging function is reliable, but the circuit structure becomes complicated and fabrication cost increases
Solution Approach 1:
The patent combines multiple delay functions into a single low-capacitance capacitor by using a pumping unit that generates gate high voltage in stages. The first pumping unit generates an intermediate high voltage, and the second pumping unit generates the final gate high voltage, with the single capacitor maintaining the voltage during the discharging period. This merging approach reduces circuit complexity while maintaining reliable discharging function.
Solution Approach 2:
The pumping units generate and store the gate high voltage in advance before the discharging operation is needed. The first pumping unit pre-charges an intermediate voltage, and the second pumping unit prepares the final gate high voltage level, allowing the single capacitor to effectively maintain this pre-generated voltage throughout the discharging period without requiring multiple capacitors.
2Loss of time
If multiple low-capacitance capacitors are used to delay discharging time, then the preset period timing is accurate, but fabrication cost increases
Solution Approach 1:
The patent merges multiple timing delay functions into a single low-capacitance capacitor by using a two-stage pumping system. The first pumping unit generates an intermediate voltage level, and the second pumping unit generates the final gate high voltage level, with the single capacitor providing the necessary time delay for the entire discharging operation. This reduces component count and fabrication cost while maintaining accurate preset period timing.
Solution Approach 2:
The first pumping unit acts as an intermediary that generates an intermediate high voltage level, which is then further pumped by the second pumping unit to achieve the final gate high voltage. This intermediary stage allows a single capacitor to effectively control the timing delay, as it operates at an optimized voltage level that reduces the charge/discharge current demands and improves timing accuracy.
3Stability of the object's composition
If multiple delay devices are used to maintain gate high voltage, then the voltage maintenance is stable, but spatial efficiency decreases
Solution Approach 1:
The patent combines multiple voltage maintenance functions into a single low-capacitance capacitor by implementing a two-stage pumping architecture. The first pumping unit generates an intermediate voltage, and the second pumping unit generates the final gate high voltage, with the single capacitor maintaining this voltage throughout the discharging period. This significantly reduces the circuit area occupied by delay devices while maintaining stable voltage levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration decreases fabrication costs, simplifies the circuit structure, and improves spatial efficiency by minimizing the number of delay devices required for maintaining the gate high voltage output.
Implementation Method 1
a first pumping unit for firstly pumping a high-potential power source voltage applied
Implementation Method 2
a second pumping unit for generating a gate high voltage by secondarily pumping the high-potential power source voltage firstly pumped in the first pumping unit
Implementation Method 3
a level shifter for shifting an input high voltage to a level corresponding to that of the gate high voltage from the second pumping unit
Implementation Method 4
a delay device, connected between input and output sides of the second pumping unit, for maintaining the gate high voltage output from the level shifter for a preset period of time
Data Source
AI summary
A liquid crystal display device and a method of driving the same is disclosed, which can minimize the number of delay devices to delay a discharging time by a preset period of time. The liquid crystal display device comprises a first pumping unit that first pumps a high-potential power source voltage applied; a second pumping unit that generates a gate high voltage by pumping the high-potential power source voltage first pumped in the first pumping unit; a level shifter that shifts an input high voltage to a level corresponding to that of the gate high voltage from the second pumping unit, and supplies the gate high voltage to a discharging circuit; and a delay device, connected between input and output sides of the second pumping unit, that maintains the gate high voltage output from the level shifter for a preset period of time.