LCD Driver Source Output Circuit Layout for Chip Size Reduction
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Solution Overview
Problem
The existing LCD drivers face challenges in miniaturization due to the constraints of the source output circuit region, where it is difficult to arrange all source output cells in the same row, leading to increased chip size and limited reduction in size, especially with the increasing demand for higher pixel density and lower power consumption for mobile applications.
Innovation Solution
The solution involves arranging source output cells in two rows and N columns, with specific electrical coupling to pads, allowing for a zigzag pattern of output pads to reduce chip size without overlapping wirings, thereby optimizing the layout and reducing the overall size of the LCD driver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If source output cells are arranged in a single row, then wiring routing is simplified, but chip size increases and miniaturization is limited
Solution Approach 1:
The patent transitions from a single-row arrangement to a two-row arrangement of source output cells. This dimensional change allows the cells to be organized more compactly, reducing the overall chip area while maintaining manageable wiring complexity through systematic pad assignment.
Solution Approach 2:
The source output cells are segmented into two rows with specific pad assignments (odd-numbered pads for first row, even-numbered pads for second row). This segmentation enables more efficient space utilization and reduces the required chip area compared to a single-row configuration.
2Quantity of substance
If the number of pixels is increased, then display resolution is improved, but the source output circuit region size is constrained more severely
Solution Approach 1:
By arranging source output cells in two rows rather than one, the patent increases the circuit region's capacity to accommodate more pixels without proportionally increasing the area. This dimensional reorganization allows higher pixel density within the same or reduced source output circuit region.
Solution Approach 2:
The patent changes the spatial arrangement parameter from single-row to two-row configuration, which alters the area-to-capacity ratio of the source output circuit region. This parameter change enables the circuit to support a greater number of pixels within constrained area boundaries.
3Area of stationary object
If source output cells are arranged in two rows, then chip size is reduced, but wiring routing complexity increases
Solution Approach 1:
The patent applies different pad assignment rules to different rows: odd-numbered pads are assigned to the first row and even-numbered pads to the second row. This localized differentiation simplifies the wiring routing within each row while maintaining overall compactness, reducing the complexity increase that would otherwise result from the two-row configuration.
Solution Approach 2:
By segmenting the pad assignments by row (odd pads for first row, even pads for second row), the patent creates manageable wiring groups that reduce routing complexity. This segmentation prevents excessive wire crossings and simplifies the connection pattern between cells and pads despite the two-row arrangement.
Data Source
AI summary
A semiconductor device has an LCD driver formed over a silicon substrate. The LCD driver is arranged in a source output circuit region and includes two or more source output cells for generating data signals and two or more output pads for receiving the data signals and sending them to the outside. The two or more pads are arranged over the silicon substrate along a row direction, and the two or more source output cells are arranged in two rows and N columns along the row direction. A source output cell arranged at an Nth column of a first row is electrically coupled to a (2N−1)th output pad. Also, a source output cell CS1 arranged at the Nth column of a second row is electrically coupled to a (2N)th output pad. The arrangement allows for a reduced chip size.


