Liquid Crystal Display Panel Driving Method Asymmetric Timing

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Solution Overview

Problem

Liquid crystal display panels are prone to uneven display, afterimage, and erroneous charging of negative polarity data due to the timing issues between gate and data signals.

Innovation Solution

A driving method for liquid crystal display panels that involves providing a first gate signal with an on period and an off period, and writing positive and negative polarity data signals during the on period, where the writing time length of the negative polarity data signal is less than that of the positive polarity data signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the writing time length of negative polarity data signal is equal to that of positive polarity data signal, then the driving method is simple, but uneven display and afterimage occur

Engineering Contradiction:
Improvedriving method simplicityVSAvoiddisplay uniformity
Core Design Contradiction:
Ease of operationVSManufacturing precision

Solution Approach 1:

The patent applies asymmetry by setting different writing time lengths for negative polarity data signals and positive polarity data signals. Specifically, the writing time length of the negative polarity data signal is set to be less than that of the positive polarity data signal, creating an asymmetric timing scheme that compensates for the different charging characteristics of liquid crystal molecules under different polarities, thereby eliminating uneven display and afterimage effects.

Inventive Principle:
Principle #4Asymmetry

2Manufacturing precision

If the writing time length of negative polarity data signal is reduced, then accurate charging is achieved, but the driving timing becomes complex

Engineering Contradiction:
Improvedata signal charging accuracyVSAvoiddriving timing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by differentiating the driving parameters for different polarity data signals. Instead of using a uniform writing time for all data signals, the patent locally optimizes the writing time for negative polarity data signals specifically, setting it shorter than that of positive polarity data signals. This localized parameter adjustment ensures accurate charging for each polarity type while maintaining overall system functionality.

Inventive Principle:
Principle #3Local quality

3Reliability

If conventional driving timing is used, then the display panel operates normally, but erroneous charging of negative polarity data occurs

Engineering Contradiction:
Improvedisplay panel operation stabilityVSAvoiddata signal charging accuracy
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by modifying the writing time parameter for negative polarity data signals. The writing time length of negative polarity data signals is changed from being equal to positive polarity data signals to being shorter than positive polarity data signals. This parameter adjustment ensures that negative polarity data is charged accurately without causing erroneous charging, while maintaining normal operation stability of the display panel.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12293735B2Driving method of liquid crystal display panel and liquid crystal display panel
Publication Date: 2025.05.06 FUZHOU BOE OPTOELECTRONICS TECH CO LTD
  • US12293735B2 patent drawing
  • US12293735B2 patent drawing
  • US12293735B2 patent drawing

AI summary

A liquid crystal display panel and a driving method of a liquid crystal display panel. The driving method includes: providing a first gate signal to a first gate line corresponding to a first row of sub-pixels among the plurality of rows of sub-pixels, in which the first gate signal includes an on period and an off period used to control the first row of sub-pixels to be turned on and off respectively; writing, during the on period of the first gate signal, a plurality of first data signals to sub-pixels among the first row of sub-pixels through the plurality of data lines, and during the on period of the first gate signal, a first writing time length of a negative polarity data signal is less than a second writing time length of a positive polarity data signal.