Liquid Crystal Driving Circuit Multiphase Clock Timing

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Solution Overview

Problem

Existing liquid crystal display devices face challenges in driving active matrix-type liquid crystal panels at high speeds due to insufficient writing time caused by narrow gate pulses, especially when using amorphous silicon TFTs, which can lead to instability in gate drivers and poor display performance.

Innovation Solution

A liquid crystal driving circuit with a clock generation circuit that generates multiphase clocks for gate drivers, ensuring effective driving of switching elements just before image signals are supplied, and separate control pulses for odd- and even-numbered scanning lines to optimize display operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the width of the source pulse is decreased to enable high-speed display, then the display speed is improved, but the width of the gate pulse is decreased accordingly, causing insufficient writing time of liquid crystal

Engineering Contradiction:
Improvedisplay speedVSAvoidwriting time of liquid crystal
Core Design Contradiction:
SpeedVSDuration of action of moving object

Solution Approach 1:

The gate pulse is advanced to start before the source pulse is supplied, preparing the switching elements in advance. This preliminary action ensures that when the source pulse arrives, the liquid crystal has sufficient writing time even though the overall pulse widths are reduced for high-speed operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The timing relationship between gate pulses and source pulses is dynamically adjusted. The gate pulse timing is shifted relative to the source pulse timing, allowing the system to maintain adequate writing time while operating at higher display speeds with reduced pulse widths.

Inventive Principle:
Principle #15Dynamics

2Area of moving object

If the number of scanning lines is increased to achieve larger pixels, then the pixel size is improved, but the gate pulse width must be reduced, causing the gate driver to become disabled

Engineering Contradiction:
Improvepixel sizeVSAvoidgate driver operation stability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

By advancing the gate pulse timing, the switching elements are activated before the corresponding source pulse arrives. This ensures reliable operation of the gate driver even when the number of scanning lines is increased and pulse widths are reduced, preventing gate driver disablement.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If amorphous silicon TFTs are used to reduce manufacturing cost, then the manufacturing cost is reduced, but the mobility is low, causing the gate driver to be disabled when gate pulse width is decreased

Engineering Contradiction:
Improvemanufacturing costVSAvoidgate driver operation stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The gate pulse is advanced to activate switching elements before the source pulse arrives. This preliminary activation compensates for the low mobility characteristics of amorphous silicon TFTs, ensuring reliable gate driver operation even with reduced gate pulse widths that result from increasing the number of scanning lines.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUSRE43850E1Liquid crystal driving circuit and liquid crystal display device
Publication Date: 2012.12.11 ONANOVICH GROUP AG LLC
  • USRE43850E1 patent drawing
  • USRE43850E1 patent drawing
  • USRE43850E1 patent drawing

AI summary

As multiphase clocks to be supplied to a first gate driver that drives odd-numbered scanning lines in a liquid crystal display region and a second gate driver that drives even-numbered scanning lines, clocks, which are effective within an effective period of the image signal just before an image signal starts to be supplied to display elements for each scanning line of the liquid crystal display region, is generated and the first and second gate drivers drive switching elements in the effective period of the clock.