Driving Circuit Signal Synthesis for LCD Pin Reduction
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Solution Overview
Problem
In liquid crystal display technology, the use of direct current (DC) voltage leads to 'direct current residual' and inconsistency in driving voltage timing, resulting in increased chip pin numbers, costs, and printed circuit board area due to the introduction of pulse signals like TP and POL.
Innovation Solution
A timing control chip and data driver chip configuration that generates and synthesizes pulse signals, allowing for the reduction of chip pins and board area by integrating pulse signals into data signals, enabling the data driver chip to decompose and control driving voltage polarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pulse signals (TP and POL) are introduced into the timing control chip and data driver chip to solve direct current residual and driving voltage timing inconsistency, then the direct current residual and timing inconsistency are resolved, but the pin number of the chips increases, resulting in increased costs and larger printed circuit board area
Solution Approach 1:
The patent merges the TP signal and POL signal transmission functions into the existing data signal transmission pathway. The timing control chip integrates pulse signal generation and modulation modules that embed timing control information within the data signal stream, eliminating the need for separate dedicated pulse signal pins. This combining approach resolves the direct current residual issue while avoiding the pin number increase that would result from separate signal lines.
2Manufacturing precision
If separate pulse signal lines are used for timing control, then driving voltage timing consistency is achieved, but the printed circuit board area increases due to additional connections
Solution Approach 1:
The data signal lines are designed to serve multiple functions: carrying both image data and timing control information (TP and POL signals). The timing control chip includes modulation modules that encode timing control data within the standard data signal format, allowing existing data signal pathways to perform dual roles. This multi-functionality approach maintains precise driving voltage timing control while avoiding additional PCB trace requirements.
3Measurement precision
If dedicated pulse signal pins are added to timing control chip and data driver chip, then timing control precision is improved, but chip costs increase due to increased pin count
Solution Approach 1:
The patent combines timing control signal transmission with the existing data signal transmission infrastructure. The timing control chip generates TP and POL pulse signals that are modulated and embedded within the data signal stream using integrated modulation modules. This approach achieves precise timing control through the combined signal pathway without requiring additional dedicated pins, thereby avoiding the cost increase associated with higher pin-count chips.
Data Source
AI summary
A timing control chip includes a pulse signal generation module for generating first and second pulse signals, a data signal sending module having a data signal including valid and invalid data segments, and a synthesis module for synthesizing the first and second pulse signals into the invalid data segment to form a synthesized data signal and then transfer it to the data signal sending module. The data signal sending module is to connect a data driver chip to make the data driver chip decompose the synthesized data signal into the first and the second pulse signal, grab a state of the second pulse signal when the first pulse signal is at a first edge and control a polarity of an outputted driving voltage according to the grabbed state of the second pulse signal. The invention further provides a data driver chip and a driving circuit.