LCD Dual Link Wiring Structure for Narrow Line Diverging Section

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Solution Overview

Problem

The increasing size and resolution of liquid crystal display (LCD) devices lead to a wider line diverging section due to the increased number of data link wires, which can result in brightness and color differences between sub-pixels, affecting picture quality.

Innovation Solution

A dual link structure is implemented where first data link wires are formed in one layer and second data link wires in another layer, allowing for a narrower line diverging section and ensuring that all sub-pixels of the same color receive signals through either the first or second data link wires to minimize resistance differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of data link wires is increased to support higher resolution, then the resolution is improved, but the line diverging section width increases causing brightness and color differences between sub-pixels

Engineering Contradiction:
ImproveresolutionVSAvoidbrightness uniformity
Core Design Contradiction:
Measurement precisionVSIllumination intensity

Solution Approach 1:

The patent applies multi-layer wiring structure where data link wires are distributed across different layers (first layer and second layer) to connect to different subsets of data lines. This vertical dimensionality change allows the line diverging section to maintain a narrower width while still accommodating the increased number of data link wires needed for higher resolution displays, thereby preventing brightness and color differences between sub-pixels.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If all data link wires are formed in a single layer, then the manufacturing process is simpler, but resistance differences occur between different data link wires affecting picture quality

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidresistance uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent segments the data link wires into two separate groups: first data link wires formed in a first layer connecting to a first subset of data lines, and second data link wires formed in a second layer connecting to a second subset of data lines. This segmentation allows for more uniform resistance characteristics across all data link wires by distributing them across different physical paths, while the manufacturing process remains manageable through systematic multi-layer fabrication.

Inventive Principle:
Principle #1Segmentation

3Illumination intensity

If the line diverging section is made narrower to improve picture quality, then brightness uniformity is improved, but the number of data link wires that can be accommodated is reduced

Engineering Contradiction:
Improvebrightness uniformityVSAvoidnumber of data link wires
Core Design Contradiction:
Illumination intensityVSQuantity of substance

Solution Approach 1:

The patent resolves this contradiction by utilizing multiple layers (vertical dimension) to accommodate data link wires. The first data link wires in the first layer and second data link wires in the second layer allow the line diverging section to maintain a narrow width profile while still supporting a large total number of data link wires through the added vertical space, thus maintaining both brightness uniformity and high resolution capability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9240149B2Liquid crystal display device and method of fabricating the same
Publication Date: 2016.01.19 LG DISPLAY CO LTD
  • US9240149B2 patent drawing
  • US9240149B2 patent drawing
  • US9240149B2 patent drawing

AI summary

Disclosed are a liquid crystal display (LCD) device and a method of fabricating the same, the LCD device having a dual link structure for reducing width of a line diverging section where data link wires diverge to come in contact with data lines. A set of data link wires are placed in a first layer and another set of data link wires are placed in a second layer so that the pitch between the data link wires can be reduced.