Liquid Crystal Display Erasing Signal Lines for Afterimage Reduction
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Solution Overview
Problem
Liquid crystal displays (LCDs) suffer from degradation issues due to unidirectional electric fields, leading to afterimages, ghost phenomena, and blurring, especially when displaying moving images, which degrade display quality.
Innovation Solution
The implementation of a liquid crystal display with erasing signal lines and storage electrode lines, along with specific thin film transistor configurations, allows for the discharge of charged data voltages and the application of erasing potentials to improve response speed and reduce image persistence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data voltages are charged and stored in pixels for the entire frame period, then the LCD can maintain stable image display, but afterimages and ghost phenomena occur due to residual charges from previous frames
Solution Approach 1:
The patent applies periodic erasing actions by introducing erasing signal lines that periodically discharge residual charges from pixels at specific timings (e.g., during horizontal synchronization periods or at predetermined intervals), thereby eliminating afterimages and ghost phenomena while maintaining stable image display during the frame period
Solution Approach 2:
The patent implements preliminary erasing actions by discharging residual charges from pixels before the next frame is displayed, using erasing signals applied at predetermined timings within the frame period, ensuring that no residual charges remain to cause afterimages or ghost effects in subsequent frames
2Device complexity
If the LCD uses conventional charging and storing method, then the structure remains simple, but response speed is slow due to long charge storage period
Solution Approach 1:
The patent segments the frame period into distinct charging periods and erasing periods by introducing separate erasing signal lines, allowing independent control of charge storage duration and enabling faster response speeds without significantly increasing overall structural complexity
Solution Approach 2:
The patent dynamically adjusts the charge storage period by controlling the timing and duration of erasing signals applied to pixels, allowing the response speed to be optimized by shortening the effective charge storage time while maintaining the necessary structure for stable image display
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the response speed of the liquid crystal display, reduces ghost and blurring effects, and improves image quality by effectively discharging charges and inserting black pixel data in each frame period.
Implementation Method 1
The LCD displays desired images by applying voltages to the field generating electrodes to generate an electric field in the liquid crystal layer and adjusting transmittance of light that passes through the liquid crystal layer by controlling intensity of the electric field
Implementation Method 2
second thin film transistors, each including a second drain electrode connected to the pixel electrode, a second gate electrode connected to the erasing signal line, and a second source electrode connected to a predetermined potential
Data Source
AI summary
A liquid crystal display includes a plurality of data lines and a plurality of gate lines disposed on a substrate in horizontal and vertical directions, respectively, pixel electrodes formed at intersecting regions of the data lines and the gate lines, a plurality of erasing signal lines disposed parallel to the gate lines, first thin film transistors, each including a first source electrode connected to one data line, a first gate electrode connected to one gate line, and a first drain electrode connected to one pixel electrode, and second thin film transistors, each including a second drain electrode connected to the pixel electrode, a second gate electrode connected to the erasing signal line, and a second source electrode connected to a predetermined potential.