LCD Frame Rate Adjustment for DC Image Sticking Prevention

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Solution Overview

Problem

Liquid crystal display (LCD) devices experience direct current image sticking and flicker due to prolonged application of voltages with the same polarity, leading to degraded display quality.

Innovation Solution

A liquid crystal display device and driving method that adjust the frame rate to a 1-fold rate in most frame periods and an i-fold accelerated rate in specific Nth frame periods, with polarity control signals inverted multiple times during the Nth frame period to prevent DC image sticking and flicker, using a frame rate adjusting circuit, timing controller, logic circuit, data driving circuit, and gate driving circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If data voltages with the same polarity are applied for a prolonged period to maintain stable display, then display stability is improved, but DC image sticking occurs due to voltage polarity accumulation

Engineering Contradiction:
Improvedisplay stabilityVSAvoidDC image sticking
Core Design Contradiction:
Stability of the object's compositionVSObject-generated harmful factors

Solution Approach 1:

The patent implements periodic polarity inversion of data voltages applied to liquid crystal cells. By systematically alternating the polarity of data voltages between adjacent liquid crystal cells or between sequential frames, the accumulation of DC voltage is prevented while maintaining stable display operation. This periodic action ensures that no single polarity dominates for an extended period, thereby eliminating DC image sticking.

Inventive Principle:
Principle #19Periodic action

2Object-generated harmful factors

If polarity inversion is applied between neighboring liquid crystal cells to reduce DC offset, then DC image sticking is reduced, but flicker occurs due to periodic brightness variations

Engineering Contradiction:
ImproveDC image stickingVSAvoidflicker
Core Design Contradiction:
Object-generated harmful factorsVSIllumination intensity

Solution Approach 1:

The patent applies different polarity inversion strategies to different regions or types of liquid crystal cells based on their specific requirements. By locally adapting the polarity inversion pattern to individual liquid crystal cells or groups, the system reduces DC offset in each cell while minimizing visible flicker effects. This localized approach allows optimization of polarity control for each cell's characteristics and position in the display.

Inventive Principle:
Principle #3Local quality

3Illumination intensity

If frame rate is increased to reduce flicker, then brightness stability is improved, but power consumption increases

Engineering Contradiction:
Improvebrightness stabilityVSAvoidpower consumption
Core Design Contradiction:
Illumination intensityVSUse of energy by moving object

Solution Approach 1:

The patent implements preliminary polarity control by pre-determining the polarity sequence of data voltages before they are applied to liquid crystal cells. By planning and optimizing the polarity inversion pattern in advance, the system achieves effective flicker reduction without requiring excessive frame rate increases. This preliminary action allows the display controller to strategically manage polarity transitions, minimizing power consumption while maintaining brightness stability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8044910B2Liquid crystal display device and method for driving thereof
Publication Date: 2011.10.25 LG DISPLAY CO LTD
  • US8044910B2 patent drawing
  • US8044910B2 patent drawing
  • US8044910B2 patent drawing

AI summary

A liquid crystal display (LCD) device and a method for driving the LCD device are disclosed. The LCD device includes a frame rate adjusting circuit for controlling a frame rate to be maintained at a 1-fold rate in frame periods other than an Nth frame period (“N” is a multiple of 8 or more), while being increased to an “i”-fold-accelerated rate (“i” is a positive integer of 2 or more) in the Nth frame period, to output reference timing signals in the frame periods other than the Nth frame period, and to output accelerated timing signals in the Nth frame period, a timing controller for generating data and gate timing control signals, based on at least one of each reference timing signal and each accelerated timing signal, and a logic circuit for accelerating a frequency of a polarity control signal in the Nth frame period.