LCD Gate Driving Circuit Layout for Reduced Panel Area

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Solution Overview

Problem

The existing gate driving circuits in liquid crystal displays occupy a large space, making it difficult to reduce the size of the liquid crystal display and improve production efficiency.

Innovation Solution

A gate driving circuit with a reduced size is achieved by incorporating a plurality of stages, including a pull-up unit, a carry output unit, and a pull-down unit, with specific voltage level transitions and aspect ratios of switching elements optimized to minimize space, and the use of dual shift registers arranged vertically on opposite sides of the gate lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If a conventional gate driving circuit with multiple stages is used, then the gate driving function is achieved, but the circuit occupies a large space on the liquid crystal panel

Engineering Contradiction:
Improvegate driving circuit areaVSAvoidgate driving function
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent merges the functions of multiple stages into a compact configuration where stages are cascaded with shared control mechanisms. The pull-up driving unit and pull-down unit are integrated within each stage, and adjacent stages share control signals, reducing the overall area while maintaining the gate driving function.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each stage in the gate driving circuit is designed to perform multiple functions: it acts as a buffer, a driver, and a control element for adjacent stages. The switching elements can operate in different modes (first mode and second mode) to achieve both pull-up and pull-down functions, reducing the need for separate dedicated components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If the gate driving circuit size is reduced, then production margin and efficiency improve, but the complexity of voltage level control increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidvoltage level control complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements preliminary charging periods before gate active periods, where capacitors are pre-charged to required voltage levels. This preliminary action simplifies the main driving phase by ensuring that voltage levels are already prepared, reducing the complexity of real-time voltage control during the active period.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The gate driving circuit operates in periodic cycles consisting of preliminary charging periods and gate active periods. This periodic operation allows the circuit to reset and prepare voltage levels systematically, making the control complexity manageable through repetitive, predictable patterns rather than continuous complex control.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20080266477A1Gate driving circuit and liquid crystal display having the same
Publication Date: 2008.10.30 LONESTAR CRYSTAL DISPLAY LLC
  • US20080266477A1 patent drawing
  • US20080266477A1 patent drawing
  • US20080266477A1 patent drawing

AI summary

A gate driving circuit has a first stage which includes: a pull-up driving unit which receives a first carry signal from a second stage and outputs a control signal having first, second, third and fourth voltages to a first node during a preliminary period, a gate active period, a first gate inactive period and a second gate inactive period, respectively; a pull-up unit which receives the control signal and outputs a gate-on signal to a second node during the gate active period; a carry output unit which receives the control signal and outputs a second carry signal to a third stage during the gate active period; and a pull-down unit which receives a gate-off signal and the second carry signal from the second stage and outputs the control signal having the fourth voltage level to the first node during the second gate inactive period.