LCD Gate Clock Synchronization for Pixel Brightness Uniformity
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Solution Overview
Problem
The existing liquid crystal display (LCD) devices suffer from a brightness difference between pixels due to a relatively short high-level interval of the first gate clock signal GCLK1 compared to the second to fourth gate clock signals, leading to deteriorated picture quality.
Innovation Solution
A driving method is introduced where the rising edge of the first gate clock signal GCLK1 is synchronized with the start signal, and subsequent gate clock signals are generated to ensure equal high-level intervals, thereby aligning the pre-charging periods of all gate lines, using a timing controller with a frame detector and gate clock signal generators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the first gate clock signal GCLK1 is generated using the conventional method with the timing controller, then the gate driver can be driven, but the high-level interval of GCLK1 becomes shorter than that of other gate clock signals, causing brightness difference between pixels
Solution Approach 1:
The patent applies preliminary action by generating the first gate clock signal GCLK1 simultaneously with the start signal Vst at the timing controller, rather than letting it be generated later by the gate driver. This ensures that GCLK1 has the same high-level interval as other gate clock signals from the beginning, preventing brightness differences in pixels along the first gate line GL1 before the display operation starts.
2Ease of manufacture
If the gate driver is directly formed on the liquid crystal panel (Gate-in-Panel structure), then integration is improved, but the first gate clock signal GCLK1 generated by the gate driver has inconsistent high-level interval compared to other gate clock signals
Solution Approach 1:
The patent uses the timing controller as an intermediary to generate the first gate clock signal GCLK1 simultaneously with the start signal Vst. This intermediary approach allows the Gate-in-Panel structure to be maintained while ensuring that GCLK1 has the correct high-level interval, as the timing controller mediates between the signal generation and the gate driver operation to eliminate the brightness inconsistency.
3Device complexity
If the first gate clock signal GCLK1 is generated by the gate driver from the start signal Vst, then the circuit configuration can be simplified, but the pre-charging period of the first gate line GL1 becomes different from other gate lines, deteriorating picture quality
Solution Approach 1:
The patent applies preliminary action by having the timing controller generate the first gate clock signal GCLK1 simultaneously with the start signal Vst before the gate driver operation begins. This ensures that the pre-charging period of the first gate line GL1 is synchronized with other gate lines, maintaining consistent picture quality across the display without requiring complex circuit modifications.
Data Source
AI summary
A driving method of an LCD device adapted to improve the quality of pictures is disclosed. The driving method includes: deriving a frame detection signal from a data enable signal and a data clock signal; simultaneously deriving a start signal and a first gate clock signal from the frame detection signal and the data clock signal; and deriving a second gate clock signal from the first gate clock signal and the data clock signal. The first gate clock signal is identical with the start signal in a start time point of enable interval.