Gate Drive Circuit for LCD Pixel Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Large screen size and high definition in flat panel displays, such as liquid crystal displays, lead to increased parasitic capacitance on gate lines, causing delays in writing scanning signals to pixel transistors, which can result in incomplete pixel transistor activation within one horizontal period.
Innovation Solution
A display device configuration with a scanning line drive circuit and a drive signal generation circuit that supplies specific potential levels to a first wire to control the gate drive signal, including a first potential lower than the off-potential, a second potential lower than the first, a third potential higher than the first, and a fourth potential higher than the on-potential of the pixel transistor, to accelerate gate drive and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate line is made long to accommodate larger screen size and higher definition, then the display area and resolution are improved, but the parasitic capacitance on the gate line increases causing slower gate drive speed
Solution Approach 1:
The gate line is divided into multiple segments with separate drive circuits. Instead of using a single long gate line driven from one end, the display panel incorporates multiple scanning line drive circuits that can drive different sections of the gate lines independently, reducing the effective length each drive circuit must control and thus reducing parasitic capacitance effects.
Solution Approach 2:
Additional drive circuits are introduced as intermediary elements between the signal source and the pixel transistors. These scanning line drive circuits act as intermediaries that can provide stronger drive capability and compensate for the RC time constant effects of long gate lines, enabling faster switching of pixel transistors despite the increased line length.
2Manufacturing precision
If the gate line is coupled to a large number of pixel transistors to increase definition, then the resolution is improved, but the total parasitic capacitance increases causing longer writing time
Solution Approach 1:
The gate lines are segmented into multiple zones, each served by a dedicated scanning line drive circuit. This segmentation reduces the number of pixel transistors that each individual drive circuit must control simultaneously, thereby reducing the total capacitive load per drive circuit and enabling faster charging/discharging of gate capacitances.
Solution Approach 2:
The drive signal parameters are optimized to achieve faster switching. The patent employs drive signals with appropriate voltage levels and waveforms that can rapidly charge and discharge the gate capacitance of pixel transistors, reducing the writing time despite the large number of connected pixels.
3Device complexity
If conventional drive signals are used, then the device complexity is kept simple, but the gate drive speed is insufficient to activate all transistors within one horizontal period
Solution Approach 1:
The scanning line drive circuits are designed to pre-charge or pre-position the gate lines before the actual pixel writing operation. By preparing the gate lines in advance with appropriate voltage levels, the system can achieve faster switching during the active writing period, ensuring all pixel transistors are activated within the horizontal period without requiring excessively complex drive waveforms.
Data Source
AI summary
The display control circuit includes a drive signal generation circuit that generates a gate drive signal, a scanning line drive circuit that supplies the gate drive signal to the scanning line, and a first wire through which the gate drive signal from the drive signal generation circuit is supplied to the scanning line drive circuit. The drive signal generation circuit includes a first potential supply circuit that supplies, to the first wire, a first potential equal to or lower than an off-potential of the pixel transistor, a second potential supply circuit that supplies, to the first wire, a second potential lower than the first potential, a third potential supply circuit that supplies, to the first wire, a third potential higher than the first potential, and a fourth potential supply circuit that supplies, to the first wire, a fourth potential equal to or higher than an on-potential of the pixel transistor.